adding support for the Asus K8V-X

This pulls it all together and adds the real board-specific code.

Confirmed to be working:
- IDE
- SATA
- floppy
- USB1.1
- USB2.0
- PS/2 keyboard
- PS/2 mouse
- serial
- parport
- sound
- ethernet
- PCI slots
- AGP
- powernow
- fan speed monitoring
- flashrom write

Change-Id: Ifb97714c2f009d688be0ca3c38ddc01599ffd799
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/390
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)

7 files changed, 112 insertions, 157 deletions

diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig
index 4975cfaebd..d297143404 100644
--- a/src/mainboard/asus/k8v-x/Kconfig
+++ b/src/mainboard/asus/k8v-x/Kconfig
@@ -1,26 +1,24 @@
-if BOARD_ASUS_A8V_E_SE
+if BOARD_ASUS_K8V_X
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select ARCH_X86
-	select CPU_AMD_SOCKET_939
-	select K8_HT_FREQ_1G_SUPPORT
+	select CPU_AMD_SOCKET_754
 	select NORTHBRIDGE_AMD_AMDK8
 	select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
 	select SOUTHBRIDGE_VIA_VT8237R
-	select SOUTHBRIDGE_VIA_K8T890
-	select SUPERIO_WINBOND_W83627EHG
+	select SOUTHBRIDGE_VIA_K8T800_OLD
+	select SUPERIO_WINBOND_W83697HF
 	select HAVE_OPTION_TABLE
 	select HAVE_ACPI_TABLES
 	select HAVE_MP_TABLE
 	select BOARD_ROMSIZE_KB_512
 	select RAMINIT_SYSINFO
-	select QRANK_DIMM_SUPPORT
 	select SET_FIDVID
 
 config MAINBOARD_DIR
 	string
-	default asus/a8v-e_se
+	default asus/k8v-x
 
 config DCACHE_RAM_BASE
 	hex
@@ -44,7 +42,11 @@ config SB_HT_CHAIN_ON_BUS0
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "A8V-E SE"
+	default "K8V-X"
+
+config AGP_APERTURE_SIZE
+	hex
+	default 0x10000000
 
 config HW_MEM_HOLE_SIZEK
 	hex
@@ -70,4 +72,4 @@ config HT_CHAIN_UNITID_BASE
 	hex
 	default 0x0
 
-endif # BOARD_ASUS_A8V_E_SE
+endif # BOARD_ASUS_K8V_X
diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c
index 218f3bb8bc..571d13618f 100644
--- a/src/mainboard/asus/k8v-x/acpi_tables.c
+++ b/src/mainboard/asus/k8v-x/acpi_tables.c
@@ -30,7 +30,7 @@
 #include <device/device.h>
 #include <device/pci_ids.h>
 #include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
+#include "southbridge/via/k8t890/k8x8xx.h"
 #include "northbridge/amd/amdk8/acpi.h"
 #include <cpu/amd/model_fxx_powernow.h>
 
diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb
index 3da93fedf7..61c5a2dfcf 100644
--- a/src/mainboard/asus/k8v-x/devicetree.cb
+++ b/src/mainboard/asus/k8v-x/devicetree.cb
@@ -1,6 +1,6 @@
 chip northbridge/amd/amdk8/root_complex		# Root complex
   device lapic_cluster 0 on			# APIC cluster
-    chip cpu/amd/socket_939			# CPU
+    chip cpu/amd/socket_754			# CPU
       device lapic 0 on end			# APIC
     end
   end
@@ -16,8 +16,26 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
           register "ide1_80pin_cable" = "1"	# 80pin cable on IDE channel 1
           register "fn_ctrl_lo" = "0"		# Enable SB functions
           register "fn_ctrl_hi" = "0xad"	# Enable SB functions
+          register "usb2_termination_set" = "1"
+          register "usb2_termination_a" = "8"
+          register "usb2_termination_b" = "8"
+          register "usb2_termination_c" = "6"
+          register "usb2_termination_d" = "6"
+          register "usb2_termination_e" = "6"
+          register "usb2_termination_f" = "6"
+          register "usb2_termination_g" = "6"
+          register "usb2_termination_h" = "6"
+          register "usb2_dpll_set" = "1"
+          register "usb2_dpll_delay" = "3"
+          register "int_efgh_as_gpio" = "1"
+          register "enable_gpo3" = "1"
+          register "disable_gpo26_gpo27" = "1"
+          register "enable_aol_2_smb_slave" = "1"
+          register "enable_gpo5" = "1"
+          register "gpio15_12_dir_output" = "1"
           device pci 0.0 on end			# HT
           device pci f.1 on end			# IDE
+          device pci 10.4 on end		# USB2
           device pci 11.0 on			# LPC
             chip drivers/generic/generic	# DIMM 0-0-0
               device i2c 50 on end
@@ -28,10 +46,9 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
             chip drivers/generic/generic	# DIMM 0-1-0
               device i2c 52 on end
             end
-            chip drivers/generic/generic	# DIMM 0-1-1
-              device i2c 53 on end
-            end
-            chip superio/winbond/w83627ehg	# Super I/O
+            chip superio/winbond/w83697hf	# Super I/O
+              register "hwmon_fan1_divisor" = "128"
+              register "hwmon_fan2_divisor" = "4"
               device pnp 2e.0 on		# Floppy
                 io 0x60 = 0x3f0
                 irq 0x70 = 6
@@ -47,35 +64,19 @@ chip northbridge/amd/amdk8/root_complex		# Root complex
                 irq 0x70 = 4
               end
               device pnp 2e.3 off		# Com2 (N/A on this board)
-                io 0x60 = 0x2f8
-                irq 0x70 = 3
-              end
-              device pnp 2e.5 off		# PS/2 keyboard & mouse (off)
-              end
-              device pnp 2e.106 off		# Serial flash interface (SFI)
-                io 0x60 = 0x100
               end
-              device pnp 2e.007 off		# GPIO 1
+              device pnp 2e.6 off		# CIR
               end
-              device pnp 2e.107 on		# Game port
-                io 0x60 = 0x201
+              device pnp 2e.7 off		# Game port/GPIO 1
               end
-              device pnp 2e.207 on		# MIDI
-                io 0x62 = 0x330
-                irq 0x70 = 0xa
+              device pnp 2e.8 off		# MIDI/GPIO 5
               end
-              device pnp 2e.307 off		# GPIO 6
-              end
-              device pnp 2e.8 off		# WDTO#, PLED
-              end
-              device pnp 2e.009 on		# GPIO 2
+              device pnp 2e.009 off		# GPIO 2
               end
               device pnp 2e.109 off		# GPIO 3
               end
               device pnp 2e.209 off		# GPIO 4
               end
-              device pnp 2e.309 on		# GPIO 5
-              end
               device pnp 2e.a off		# ACPI
               end
               device pnp 2e.b on		# Hardware monitor
diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl
index 16ad92c077..25b7460b20 100644
--- a/src/mainboard/asus/k8v-x/dsdt.asl
+++ b/src/mainboard/asus/k8v-x/dsdt.asl
@@ -84,6 +84,8 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE  ", "COREBOOT", 1)
 
 			/* PCI Routing Table */
 			Name (_PRT, Package () {
+				Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */
+				Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
 				Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */
 				Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
 				Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
@@ -96,88 +98,23 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE  ", "COREBOOT", 1)
 				Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
 				Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
 				Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
+				Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */
+				Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 },
+				Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 },
+				Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 },
+				Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */
+				Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 },
+				Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 },
+				Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 },
+				Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */
 				Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */
 				Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
 				Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
 				Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
 				Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
-				Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
-				Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */
-				Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
-				Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
-				Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
-				Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
-				Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
-				Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
-				Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
-				Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B }  /* IRQ43 */
+				Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }  /* AC97, MC97 */
 			})
 
-			Device (PEGG)
-			{
-				Name (_ADR, 0x00020000)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x02)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
-				})
-			}
-
-			Device (PEX0)
-			{
-				Name (_ADR, 0x00030000)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x03)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
-				})
-			}
-
-			Device (PEX1)
-			{
-				Name (_ADR, 0x00030001)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x04)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
-				})
-			}
-
-			Device (PEX2)
-			{
-				Name (_ADR, 0x00030002)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x05)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
-				})
-			}
-
-			Device (PEX3)
-			{
-				Name (_ADR, 0x00030003)
-				Name (_UID, 0x00)
-				Name (_BBN, 0x06)
-				Name (_PRT, Package () {
-					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */
-					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },
-					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },
-					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },
-				})
-			}
-
 			Device (ISA) {
 				Name (_ADR, 0x00110000)
 
diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c
index b70f396987..3e294b8916 100644
--- a/src/mainboard/asus/k8v-x/mainboard.c
+++ b/src/mainboard/asus/k8v-x/mainboard.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,8 +22,43 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <arch/io.h>
+#include "southbridge/via/vt8237r/vt8237r.h"
 #include "chip.h"
 
+u32 vt8237_ide_80pin_detect(struct device *dev)
+{
+	device_t lpc_dev;
+	u16 acpi_io_base;
+	u32 gpio_in;
+	u32 res;
+
+	lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
+				PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
+	if (!lpc_dev)
+		return 0;
+
+	acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1;
+	if (!acpi_io_base)
+		return 0;
+
+	/* select function GPIO29 for pin AB9 */
+	pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08);
+
+	gpio_in = inl(acpi_io_base + 0x48);
+	/* bit 29 for primary port, clear if unconnected or 80-pin cable */
+	res  = gpio_in & (1<<29) ? 0 : VT8237R_IDE0_80PIN_CABLE;
+	/* bit 8 for secondary port, clear if unconnected or 80-pin cable */
+	res |= gpio_in & (1<<8) ? 0 : VT8237R_IDE1_80PIN_CABLE;
+
+	printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary",
+		res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40);
+	printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary",
+		res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40);
+
+	return res;
+}
+
 struct chip_operations mainboard_ops = {
-	CHIP_NAME("ASUS A8V-E SE Mainboard")
+	CHIP_NAME("ASUS K8V-X Mainboard")
 };
diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c
index 999dd6cd33..673dfbefbe 100644
--- a/src/mainboard/asus/k8v-x/mptable.c
+++ b/src/mainboard/asus/k8v-x/mptable.c
@@ -22,7 +22,7 @@
 #include <arch/smp/mpspec.h>
 #include <arch/ioapic.h>
 #include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
+#include "southbridge/via/k8t890/k8x8xx.h"
 
 static void *smp_write_config_table(void *v)
 {
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index 4e08859746..014ce68b1f 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -40,7 +40,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/early_ht.c"
-#include "superio/winbond/w83627ehg/early_serial.c"
+#include "superio/winbond/w83697hf/early_serial.c"
 #include "southbridge/via/vt8237r/early_smbus.c"
 #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */
 #include "cpu/x86/mtrr/earlymtrr.c"
@@ -48,9 +48,7 @@ unsigned int get_sbdn(unsigned bus);
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include <spd.h>
 
-#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
-#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
+#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
 static void activate_spd_rom(const struct mem_controller *ctrl) { }
@@ -105,52 +103,25 @@ static void sio_init(void)
 	u8 reg;
 
 	pnp_enter_ext_func_mode(SERIAL_DEV);
-	/* We have 24MHz input. */
 	reg = pnp_read_config(SERIAL_DEV, 0x24);
-	pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
-	/* We have GPIO for KB/MS pin. */
-	reg = pnp_read_config(SERIAL_DEV, 0x2a);
-	pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
-	/* We have all RESTOUT and even some reserved bits, too. */
-	reg = pnp_read_config(SERIAL_DEV, 0x2c);
-	pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
-	pnp_exit_ext_func_mode(SERIAL_DEV);
-
-	pnp_enter_ext_func_mode(ACPI_DEV);
-	pnp_set_logical_device(ACPI_DEV);
-	/*
-	 * Set the delay rising time from PWROK_LP to PWROK_ST to
-	 * 300 - 600ms, and 0 to vice versa.
-	 */
-	reg = pnp_read_config(ACPI_DEV, 0xe6);
-	pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
-	/* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
-	reg = pnp_read_config(ACPI_DEV, 0xe4);
-	pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
-	pnp_exit_ext_func_mode(ACPI_DEV);
-
-	pnp_enter_ext_func_mode(GPIO_DEV);
-	pnp_set_logical_device(GPIO_DEV);
-	/* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
-	pnp_write_config(GPIO_DEV, 0x30, 0x09);	/* Enable GPIO 2 & GPIO 5. */
-	pnp_write_config(GPIO_DEV, 0xe2, 0x00);	/* No inversion */
-	pnp_write_config(GPIO_DEV, 0xe5, 0x00);	/* No inversion */
-	pnp_write_config(GPIO_DEV, 0xe3, 0x03);	/* 0000 0011, 0=output 1=input */
-	pnp_write_config(GPIO_DEV, 0xe0, 0xde);	/* 1101 1110, 0=output 1=input */
-	pnp_write_config(GPIO_DEV, 0xe1, 0x01);	/* Set output val. */
-	pnp_write_config(GPIO_DEV, 0xe4, 0xb4);	/* Set output val (1011 0100). */
-	pnp_exit_ext_func_mode(GPIO_DEV);
+	/* 4 Mbit flash */
+	reg = (reg & ~0x30) | 0x20;
+	/* We have 24MHz input. */
+	reg &= ~0x40;
+	/* enable MEMW#, so flash can be written */
+	reg |= 0x08;
+	pnp_write_config(SERIAL_DEV, 0x24, reg);
 }
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
 		// Node 0
-		DIMM0, DIMM2, 0, 0,
-		DIMM1, DIMM3, 0, 0,
+		DIMM0, DIMM1, DIMM2, 0,
+		0, 0, 0, 0,
 		// Node 1
-		DIMM4, DIMM6, 0, 0,
-		DIMM5, DIMM7, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
 	};
 	unsigned bsp_apicid = 0;
 	int needs_reset = 0;
@@ -158,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
 	sio_init();
-	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 	enable_rom_decode();
 
@@ -173,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	// FIXME why is this executed again? --->
 	sio_init();
-	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	console_init();
 	enable_rom_decode();
 	// <--- FIXME why is this executed again?
@@ -209,7 +180,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		soft_reset();
 	}
 
-	/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
+	/* the HT settings needs to be OK, because link freq change may cause HT disconnect */
+	vt8237_sb_enable_fid_vid();
 	enable_fid_change();
 	init_fidvid_bsp(bsp_apicid);
 
@@ -220,6 +192,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 
 	enable_smbus();
+
+	/* this seems to be some GPIO on the SMBus--in any case, setting these
+	 * two bits reduces the pullup impedance of the bus lines and is required
+	 * in order to be able to read SPD info */
+	smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80);
+	smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10);
+
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 	post_cache_as_ram();
 }