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authorStefan Reinauer <reinauer@chromium.org>2015-01-05 13:02:32 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-01-06 20:16:47 +0100
commit069f4766a013929fa7570194925978b55b8253df (patch)
tree1b24e081953009c0899ce1fb515a43d3aa402600 /src/mainboard/asus/k8v-x
parent5491ca23fc2a0dc69ab6efe149050463207462b8 (diff)
downloadcoreboot-069f4766a013929fa7570194925978b55b8253df.tar.xz
mainboard: Drop print_ implementation from non-romcc boards
Because we had no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the mainboard code to use printk() on all non-ROMCC boards. Change-Id: I2383f24343fc2041fef4af65d717d754ad58425e Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/8111 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/asus/k8v-x')
-rw-r--r--src/mainboard/asus/k8v-x/romstage.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index 51276188e8..048da22fce 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -63,7 +63,7 @@ void soft_reset(void)
uint8_t tmp;
set_bios_reset();
- print_debug("soft reset\n");
+ printk(BIOS_DEBUG, "soft reset\n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -111,7 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
enable_rom_decode();
- print_info("now booting... fallback\n");
+ printk(BIOS_INFO, "now booting... fallback\n");
/* Is this a CPU only reset? Or is this a secondary CPU? */
if (!cpu_init_detectedx && boot_cpu()) {
@@ -120,7 +120,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain();
}
- print_info("now booting... real_main\n");
+ printk(BIOS_INFO, "now booting... real_main\n");
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@ -132,7 +132,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
wait_all_core0_started();
- print_info("now booting... Core0 started\n");
+ printk(BIOS_INFO, "now booting... Core0 started\n");
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched. */
@@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= k8t890_early_setup_ht();
if (needs_reset) {
- print_debug("ht reset -\n");
+ printk(BIOS_DEBUG, "ht reset -\n");
soft_reset();
}