diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-10-12 10:54:30 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-18 12:51:26 +0000 |
| commit | 400ce55566caa541304b2483e61bcc2df941998c (patch) | |
| tree | 4e0cbf4aef7fb00a9c40327075ffa9737e56b104 /src/mainboard/asus/kfsn4-dre | |
| parent | e64a585374de88ea896ed517445a34986aa321b9 (diff) | |
| download | coreboot-400ce55566caa541304b2483e61bcc2df941998c.tar.xz | |
cpu/amd: Use common AMD's MSR
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/mainboard/asus/kfsn4-dre')
| -rw-r--r-- | src/mainboard/asus/kfsn4-dre/romstage.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 036f136f06..a6fd8b2291 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -35,6 +35,7 @@ #include <cbmem.h> #include <cpu/amd/model_10xxx_rev.h> #include <cpu/amd/car.h> +#include <cpu/amd/msr.h> #include <southbridge/nvidia/ck804/early_smbus.h> #include <delay.h> #include <cpu/x86/lapic.h> @@ -256,7 +257,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) wait_all_core0_started(); if (IS_ENABLED(CONFIG_SET_FIDVID)) { - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); @@ -270,7 +271,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3A); /* show final fid and vid */ - msr = rdmsr(0xc0010071); + msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); } |