mainboard/asus/kfsn4-dre: Enable BIOS recovery jumper

The ASUS KFSN4-DRE has a physical BIOS recovery jumper;
force coreboot into fallback mode if that jumper is set.

Change-Id: I513299c3e3261fc76133a49813685d48c53a172a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/9156
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>

3 files changed, 92 insertions, 0 deletions

diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig
index a7ac3693fd..47fccdace4 100644
--- a/src/mainboard/asus/kfsn4-dre/Kconfig
+++ b/src/mainboard/asus/kfsn4-dre/Kconfig
@@ -28,6 +28,10 @@ config MAINBOARD_DIR
 	string
 	default asus/kfsn4-dre
 
+config BOOTBLOCK_MAINBOARD_INIT
+	string
+	default "mainboard/asus/kfsn4-dre/bootblock.c"
+
 config DCACHE_RAM_BASE
 	hex
 	default 0xc4000
diff --git a/src/mainboard/asus/kfsn4-dre/bootblock.c b/src/mainboard/asus/kfsn4-dre/bootblock.c
new file mode 100644
index 0000000000..45206cb629
--- /dev/null
+++ b/src/mainboard/asus/kfsn4-dre/bootblock.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <pc80/mc146818rtc.h>
+
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627thg/w83627thg.h>
+
+#define GPIO_DEV PNP_DEV(0x2e, W83627THG_GPIO3)
+
+#define WINBOND_ENTRY_KEY 0x87
+#define WINBOND_EXIT_KEY 0xAA
+
+/* Enable configuration: pass entry key '0x87' into index port dev. */
+static void pnp_enter_conf_state(pnp_devfn_t dev)
+{
+	u16 port = dev >> 8;
+	outb(WINBOND_ENTRY_KEY, port);
+	outb(WINBOND_ENTRY_KEY, port);
+}
+
+/* Disable configuration: pass exit key '0xAA' into index port dev. */
+static void pnp_exit_conf_state(pnp_devfn_t dev)
+{
+	u16 port = dev >> 8;
+	outb(WINBOND_EXIT_KEY, port);
+}
+
+uint8_t bootblock_read_recovery_jumper(pnp_devfn_t dev)
+{
+	uint8_t recovery_enabled = 0;
+
+	pnp_enter_conf_state(dev);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 1);						/* Enable GPIO3 */
+	pnp_write_config(dev, 0xf0, 0xff);				/* Set GPIO3 to input */
+	recovery_enabled = !(pnp_read_config(dev, 0xf1) & 0x08);	/* Read GP33 */
+	pnp_exit_conf_state(dev);
+
+	return recovery_enabled;
+}
+
+void bootblock_mainboard_init(void)
+{
+	uint8_t recovery_enabled;
+	unsigned char addr;
+	unsigned char byte;
+
+	recovery_enabled = bootblock_read_recovery_jumper(GPIO_DEV);
+	if (recovery_enabled) {
+#if CONFIG_USE_OPTION_TABLE
+		/* Clear NVRAM checksum */
+		for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
+			cmos_write(0x0, addr);
+		}
+
+		/* Set fallback boot */
+		byte = cmos_read(RTC_BOOT_BYTE);
+		byte &= 0xfc;
+		cmos_write(byte, RTC_BOOT_BYTE);
+#else
+		/* FIXME
+		 * Figure out how to recover if the option table is not available
+		 */
+#endif
+	}
+}
\ No newline at end of file
diff --git a/src/mainboard/asus/kfsn4-dre/spd_notes.txt b/src/mainboard/asus/kfsn4-dre/spd_notes.txt
index d7440f09d1..9287a5f75a 100644
--- a/src/mainboard/asus/kfsn4-dre/spd_notes.txt
+++ b/src/mainboard/asus/kfsn4-dre/spd_notes.txt
@@ -47,6 +47,9 @@ Power LED (-) is connected to U15 (SuperIO) pin 64 via U4 pins 5,6 and a small M
 ID LED (-) is connected to a ??? via U4 pins 1,2,3,4 and U77 pins 5,6
 It appears that setting U15 (SuperIO) pin 88 LOW will override the ID LED and force it ON
 
+RECOVERY2 middle pin is connected to U15 (SuperIO) pin 89
+Normal is HIGH, recovery is LOW.
+
 PCIe slot WAKE# connects to U7 pin E23 (PCIE_WAKE#)
 
 CPU_WARN1 is driven by (???) via a simple buffer (U13 pin 10)