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author | Tobias Diedrich <ranma+coreboot@tdiedrich.de> | 2010-11-24 20:03:09 +0000 |
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committer | Tobias Diedrich <ranma@tdiedrich.de> | 2010-11-24 20:03:09 +0000 |
commit | 48ae6086da64eb260c6eed676c593cdcd0957fbf (patch) | |
tree | f70d55ae2a05576cd988c9ee07c770b49dae1617 /src/mainboard/asus/m2v/romstage.c | |
parent | ba9f0b30fb3d2081e30c8957194f3a0a202bc2ef (diff) | |
download | coreboot-48ae6086da64eb260c6eed676c593cdcd0957fbf.tar.xz |
S3 support for ASUS M2V
This adds the board-specific parts for S3 support on the M2V board.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6122 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asus/m2v/romstage.c')
-rw-r--r-- | src/mainboard/asus/m2v/romstage.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 4c86f55657..3176c39866 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -73,6 +73,15 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" + +// Now, this needs to be included because it relies on the symbol +// __PRE_RAM__ being set during CAR stage (in order to compile the +// BSS free versions of the functions). Either rewrite the code +// to be always BSS free, or invent a flag that's better suited than +// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) +// +#include "lib/cbmem.c" + #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/resourcemap.c" @@ -242,6 +251,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rom_decode(); m2v_bus_init(); m2v_it8712f_gpio_init(); + it8712f_enable_3vsbsw(); printk(BIOS_INFO, "now booting... \n"); |