mb/*/*: Drop AMDFAM10 mainboards

Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: Ic00ca18de3d73a17041a3a2839307149ad7902b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36961
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 116 deletions

diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c
deleted file mode 100644
index 66da65baad..0000000000
--- a/src/mainboard/asus/m4a78-em/mainboard.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_def.h>
-#include <southbridge/amd/sb700/sb700.h>
-#include <southbridge/amd/sb700/smbus.h>
-#include <southbridge/amd/rs780/rs780.h>
-
-void set_pcie_dereset(void)
-{
-	u8 byte;
-	u16 word;
-	struct device *sm_dev;
-	/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
-	/* set 0 to bit2 :disable GPM8 as AZ_RST output */
-	byte = pm_ioread(0x8d);
-	byte &= ~((1 << 1) | (1 << 2));
-	pm_iowrite(0x8d, byte);
-
-	/* set the GPM8 and GPM9 output enable and the value to 1 */
-	byte = pm_ioread(0x94);
-	byte &= ~((1 << 2) | (1 << 3));
-	byte |=  ((1 << 0) | (1 << 1));
-	pm_iowrite(0x94, byte);
-
-	/* set the GPIO65 output enable and the value is 1 */
-	sm_dev = pcidev_on_root(0x14, 0);
-	word = pci_read_config16(sm_dev, 0x7e);
-	word |= (1 << 0);
-	word &= ~(1 << 4);
-	pci_write_config16(sm_dev, 0x7e, word);
-}
-
-void set_pcie_reset(void)
-{
-	u8 byte;
-	u16 word;
-	struct device *sm_dev;
-
-	/* set 0 to bit1 :disable GPM9 as SLP_S2 output */
-	/* set 0 to bit2 :disable GPM8 as AZ_RST output */
-	byte = pm_ioread(0x8d);
-	byte &= ~((1 << 1) | (1 << 2));
-	pm_iowrite(0x8d, byte);
-
-	/* set the GPM8 and GPM9 output enable and the value to 0 */
-	byte = pm_ioread(0x94);
-	byte &= ~((1 << 2) | (1 << 3));
-	byte &= ~((1 << 0) | (1 << 1));
-	pm_iowrite(0x94, byte);
-
-	/* set the GPIO65 output enable and the value is 0 */
-	sm_dev = pcidev_on_root(0x14, 0);
-	word = pci_read_config16(sm_dev, 0x7e);
-	word &= ~(1 << 0);
-	word &= ~(1 << 4);
-	pci_write_config16(sm_dev, 0x7e, word);
-}
-
-/*
- * justify the dev3 is exist or not
- * NOTE: This just copied from AMD Tilapia code.
- * It is completely unknown if it will work at all for this board.
- */
-int is_dev3_present(void)
-{
-	u16 word;
-	struct device *sm_dev;
-
-	/* access the smbus extended register */
-	sm_dev = pcidev_on_root(0x14, 0);
-
-	/* put the GPIO68 output to tristate */
-	word = pci_read_config16(sm_dev, 0x7e);
-	word |= 1 << 6;
-	pci_write_config16(sm_dev, 0x7e,word);
-
-	/* read the GPIO68 input status */
-	word = pci_read_config16(sm_dev, 0x7e);
-
-	return !(word & (1 << 10));
-}
-
-
-/*************************************************
-* enable the dedicated function in this board.
-* This function called early than rs780_enable.
-*************************************************/
-static void mainboard_enable(struct device *dev)
-{
-	printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
-
-	set_pcie_dereset();
-	/* get_ide_dma66(); */
-	/* set_thermal_config(); */
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};