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| author | efdesign98 <efdesign98@gmail.com> | 2011-07-20 12:37:58 -0600 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2011-07-22 00:20:59 +0200 |
| commit | 00c8c4a31632150fa711493f39e727da950ebe9f (patch) | |
| tree | f3bad2e78ddb6999ad551a73f05c049a266a14ab /src/mainboard/asus/m4a785-m | |
| parent | 09ea8ea1a74d56a37755cec52077555b91f9e5b4 (diff) | |
| download | coreboot-00c8c4a31632150fa711493f39e727da950ebe9f.tar.xz | |
Update AMD SR5650 and SB700
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes. The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements. This particular change
affects all mainboards that use the SB700, and their changes are
include herein. These mainboards are:
Advansus a785e,
AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
Asrock 939a785gmh,
Asus m4a78-em, m4a785-m,
Gigabyte ma785gm,
Iei Kino-780am2-fam10
Jetway pa78vm5
Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.
Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/mainboard/asus/m4a785-m')
| -rw-r--r-- | src/mainboard/asus/m4a785-m/mainboard.c | 9 | ||||
| -rw-r--r-- | src/mainboard/asus/m4a785-m/romstage.c | 5 |
2 files changed, 5 insertions, 9 deletions
diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c index a5a15e84d9..e490f31886 100644 --- a/src/mainboard/asus/m4a785-m/mainboard.c +++ b/src/mainboard/asus/m4a785-m/mainboard.c @@ -24,16 +24,13 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include <southbridge/amd/sb700/sb700.h> +#include "southbridge/amd/sb700/sb700.h" +#include "southbridge/amd/sb700/smbus.h" #include "chip.h" #define ADT7461_ADDRESS 0x4C #define ARA_ADDRESS 0x0C /* Alert Response Address */ -extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); -extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, - u8 val); - #define ADT7461_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) #define ARA_read_byte(address) \ @@ -41,8 +38,6 @@ extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, #define ADT7461_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) -#define SMBUS_IO_BASE 0x6000 - uint64_t uma_memory_base, uma_memory_size; void set_pcie_dereset(void); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 0675ee670f..b14a7c6845 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -48,14 +48,15 @@ #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/early_setup.c" +#include "southbridge/amd/sb700/sb700.h" +#include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdfam10/debug.c" static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) { - return smbus_read_byte(device, address); + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } #include "northbridge/amd/amdfam10/amdfam10.h" |