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author | Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> | 2011-11-27 15:58:38 +0100 |
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committer | Patrick Georgi <patrick@georgi-clan.de> | 2011-12-02 17:27:51 +0100 |
commit | 96ffc55bfd3fa5500fbe6b315f81462d421fb1f1 (patch) | |
tree | 7e66e116f19d7f5e3723c1a0901525e91e6784ce /src/mainboard/asus/m4a785t-m/Kconfig | |
parent | 188a9b0a7fa0509a5d03a839073670054f0ed0f6 (diff) | |
download | coreboot-96ffc55bfd3fa5500fbe6b315f81462d421fb1f1.tar.xz |
Add ASUS M4A785T-M mainboard support
This mainboard is very similar to the M4A785-M, but it has
DDR3 instead of DDR2.
That's why most of the code was copied or included from
the m4a785-m directory
Notable changes between the two mainboards include:
* the selection of the last microcode (mc_patch_010000b6.h)
which made it pass the CPU init.
* the selection of DDR3 which made it pass the ram init
This change was tested with the Trisquel 5.0 GNU/Linux distribution
which uses the linux-libre version 2.6.38-12-generic
The mainboard boots fine, however some special care is required for
the onboard sound CODEC, and the onboard video chip:
* the onboard sound CODEC(snd-hda-* has to be blacklisted), the issue
is the same than the ASUS M4A785-M mainboard:
It causes a flood of interupts which prevents booting
* The internal video chip currently requires pci=nocrs, else
the graphics are frozen as soon as the radeon module loads,
and dmesg would print the following(the card only has 256M,
and the mainboard was equiped with 2G of RAM):
[ 3.674762] [drm] radeon: 3584M of VRAM memory ready
[ 3.679863] [drm] radeon: 512M of GTT memory ready.
instead of :
[ 45.876088] [drm] radeon: 256M of VRAM memory ready
[ 45.876089] [drm] radeon: 512M of GTT memory ready.
* The screen(both VGA and HDMI) flickers at high resolution
* Sometimes the computer freeze while changing the resolution
(even the serial console stops responding)
The following peripherals were tested:
* The ath9k PCI wireless card was tested
* The SATA hard disk works fine
* the USB keyboard and mouse work fine
* htop see 2 cores
* serial port works under coreboot and GNU/Linux
* power off and reboot works
CPU frequency cannot be changed yet, this is addressed
in a new commit.
More detail are available here:
http://www.coreboot.org/ASUS_M4A785T-M
dmesg is available here:
http://www.coreboot.org/pipermail/coreboot/2011-November/067604.html
The mailing list thread on the graphic problem is here:
http://www.coreboot.org/pipermail/coreboot/2011-November/067466.html
Change-Id: I5df0bc1f9f0071b1e1ee7c8a356bf517aa8cf732
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/457
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/asus/m4a785t-m/Kconfig')
-rw-r--r-- | src/mainboard/asus/m4a785t-m/Kconfig | 86 |
1 files changed, 86 insertions, 0 deletions
diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig new file mode 100644 index 0000000000..e3893b28fc --- /dev/null +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -0,0 +1,86 @@ +if BOARD_ASUS_M4A785TM + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_AM3 + select DIMM_DDR3 + select DIMM_REGISTERED + select NORTHBRIDGE_AMD_AMDFAM10 + select SOUTHBRIDGE_AMD_RS780 + select SOUTHBRIDGE_AMD_SB700 + select SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT + select SUPERIO_ITE_IT8712F + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_HARD_RESET + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select LIFT_BSP_APIC_ID + select SERIAL_CPU_INIT + select AMDMCT + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + select RAMINIT_SYSINFO + select ENABLE_APIC_EXT_ID + select GFXUMA + select QRANK_DIMM_SUPPORT + +config MAINBOARD_DIR + string + default asus/m4a785t-m + +config APIC_ID_OFFSET + hex + default 0x0 + +config MAINBOARD_PART_NUMBER + string + default "M4A785T-M" + +config MAX_CPUS + int + default 8 + +config MAX_PHYSICAL_CPUS + int + default 2 + +config MEM_TRAIN_SEQ + int + default 2 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x1 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +config IRQ_SLOT_COUNT + int + default 19 + +config AMD_UCODE_PATCH_FILE + string + default "mc_patch_010000c4.h" + +config RAMTOP + hex + default 0x2000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config RAMBASE + hex + default 0x200000 + +endif |