amdfam10: Perform major include ".c" cleanup

Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)

This patch separates the build into separate .o modules
and links them accordingly.

Currently compiles and links all fam10 roms without
breaking other roms.

Both DDR2 and DDR3 have been completed

TESTED on REACTS: passes all boot tests for 2 boards
 ASUS KGPE-D16
 ASUS KFSN4-DRE

Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
 advansus/a785e-i
 asus/m5a88-v
 avalue/eax-785e

A followup patch may be required to fix the above boards.
See FIXME, XXX tags

Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>

5 files changed, 33 insertions, 47 deletions

diff --git a/src/mainboard/asus/m5a88-v/Kconfig b/src/mainboard/asus/m5a88-v/Kconfig
index 8f2ede13ee..9bb89656a4 100644
--- a/src/mainboard/asus/m5a88-v/Kconfig
+++ b/src/mainboard/asus/m5a88-v/Kconfig
@@ -7,7 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select DIMM_REGISTERED
 	select NORTHBRIDGE_AMD_AMDFAM10
 	select SOUTHBRIDGE_AMD_RS780
-	select SOUTHBRIDGE_AMD_CIMX_SB800
+	select SOUTHBRIDGE_AMD_SB800
 	select SUPERIO_ITE_IT8721F
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
diff --git a/src/mainboard/asus/m5a88-v/Makefile.inc b/src/mainboard/asus/m5a88-v/Makefile.inc
deleted file mode 100644
index 7b6a8e6ce5..0000000000
--- a/src/mainboard/asus/m5a88-v/Makefile.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-
-#SB800 CIMx share AGESA V5 lib code
-ifneq ($(CONFIG_CPU_AMD_AGESA),y)
- AGESA_ROOT ?= src/vendorcode/amd/agesa/f14
- romstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c
- ramstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c
-
- AGESA_INC := -I$(AGESA_ROOT)/ \
-	      -I$(AGESA_ROOT)/../common \
-	      -I$(AGESA_ROOT)/Include \
-	      -I$(AGESA_ROOT)/Proc/IDS/ \
-	      -I$(AGESA_ROOT)/Proc/CPU/ \
-	      -I$(AGESA_ROOT)/Proc/CPU/Family
-
- CFLAGS_common += $(AGESA_INC)
-endif
diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c
index 941ba26afe..3e20044e68 100644
--- a/src/mainboard/asus/m5a88-v/mainboard.c
+++ b/src/mainboard/asus/m5a88-v/mainboard.c
@@ -20,8 +20,6 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
-#include "SBPLATFORM.h"
-
 
 u8 is_dev3_present(void);
 void set_pcie_dereset(void);
@@ -34,14 +32,14 @@ void enable_int_gfx(void)
 	volatile u8 *gpio_reg;
 
 	/* make sure the MMIO(fed80000) is accessible */
-	RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
+	// FIXME: RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
 
-	gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
+	gpio_reg = (volatile u8 *)0xFED80000 + 0xD00; /* IoMux Register */
 
 	*(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
 	*(gpio_reg + 170) = 0x1; /* gpio_gate */
 
-	gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */
+	gpio_reg = (volatile u8 *)0xFED80000 + 0x100; /* GPIO Registers */
 
 	*(gpio_reg + 0x6) = 0x8;
 	*(gpio_reg + 170) = 0x0;
diff --git a/src/mainboard/asus/m5a88-v/mptable.c b/src/mainboard/asus/m5a88-v/mptable.c
index 5216783a31..7df8be3e32 100644
--- a/src/mainboard/asus/m5a88-v/mptable.c
+++ b/src/mainboard/asus/m5a88-v/mptable.c
@@ -20,7 +20,6 @@
 #include <string.h>
 #include <stdint.h>
 #include <cpu/amd/amdfam10_sysconf.h>
-#include <SBPLATFORM.h>
 
 extern int bus_isa;
 extern u8 bus_rs780[11];
@@ -42,7 +41,7 @@ u8 intr_data[] = {
 static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;
-	u32 dword;
+	u32 dword = 0;
 	u8 byte;
 
 	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -56,7 +55,7 @@ static void *smp_write_config_table(void *v)
 	mptable_write_buses(mc, NULL, &bus_isa);
 
 	/* I/O APICs:   APIC ID Version State   Address */
-	ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
+	// FIXME: ReadPMIO(SB_PMIOA_REG34, AccWidthUint32, &dword);
 	dword &= 0xFFFFFFF0;
 	smp_write_ioapic(mc, apicid_sb800, 0x11,(void *) dword);
 
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 28867ee12f..d11f98a039 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -17,7 +17,6 @@
 #define SYSTEM_TYPE 1	/* DESKTOP */
 //#define SYSTEM_TYPE 2	/* MOBILE */
 
-//used by incoherent_ht
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 0
 
@@ -32,42 +31,43 @@
 #include <console/console.h>
 #include <timestamp.h>
 #include <cpu/amd/model_10xxx_rev.h>
-#include <northbridge/amd/amdfam10/raminit.h>
-#include <northbridge/amd/amdfam10/amdfam10.h>
 #include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdfam10/reset_test.c"
 #include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8721f/it8721f.h>
 #include <cpu/amd/mtrr.h>
-#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include <cpu/amd/car.h>
+#include <southbridge/amd/sb800/smbus.h>
+#include <northbridge/amd/amdfam10/raminit.h>
+#include <northbridge/amd/amdht/ht_wrapper.h>
+#include <cpu/amd/family_10h-family_15h/init_cpus.h>
+#include <arch/early_variables.h>
+#include <cbmem.h>
 #include "southbridge/amd/rs780/early_setup.c"
-#include <sb_cimx.h>
-#include <SBPLATFORM.h> /* SB OEM constants */
-#include <southbridge/amd/cimx/sb800/smbus.h>
-#include "northbridge/amd/amdfam10/debug.c"
+#include "southbridge/amd/sb800/early_setup.c"
+#include "spd.h"
+#include <reset.h>
+
+#include "resourcemap.c"
+#include "cpu/amd/quadcore/quadcore.c"
+
+#define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1)
+
+void activate_spd_rom(const struct mem_controller *ctrl);
+int spd_read_byte(unsigned device, unsigned address);
+extern struct sys_info sysinfo_car;
 
-static void activate_spd_rom(const struct mem_controller *ctrl)
+void activate_spd_rom(const struct mem_controller *ctrl)
 {
 }
 
-static int spd_read_byte(u32 device, u32 address)
+int spd_read_byte(u32 device, u32 address)
 {
 	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
 
-#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
-#include "northbridge/amd/amdfam10/pci.c"
-#include "resourcemap.c"
-#include "cpu/amd/quadcore/quadcore.c"
-#include <cpu/amd/microcode.h>
-#include "cpu/amd/family_10h-family_15h/init_cpus.c"
-#include "northbridge/amd/amdfam10/early_ht.c"
-#include "spd.h"
-#include <reset.h>
 
-#define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	struct sys_info *sysinfo = &sysinfo_car;
@@ -86,7 +86,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		enumerate_ht_chain();
 
 		//enable port80 decoding and southbridge poweron init
-		sb_Poweron_Init();
+		sb800_lpc_init();
+		sb800_pci_port80();
 	}
 
 	post_code(0x30);
@@ -157,12 +158,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	/* run _early_setup before soft-reset. */
 	rs780_early_setup();
+	sb800_early_setup();
 
 #if CONFIG_SET_FIDVID
 	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 	post_code(0x39);
 
+	enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+
 	if (!warm_reset_detect(0)) {			// BSP is node 0
 		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 	} else {
@@ -218,6 +222,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 //	die("After MCT init before CAR disabled.");
 
 	rs780_before_pci_init();
+	sb800_before_pci_init();
 
 	post_code(0x42);
 	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.