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authorUwe Hermann <uwe@hermann-uwe.de>2010-10-13 08:21:44 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-10-13 08:21:44 +0000
commitab50d62ea6867712eca79e9f0770d6ac35f72ce1 (patch)
tree0484728745bb1699e3e4fd2a8f623d508e502661 /src/mainboard/asus/mew-vm
parent51eafdeae621f1b04db51c3b4a690fa993aa48a0 (diff)
downloadcoreboot-ab50d62ea6867712eca79e9f0770d6ac35f72ce1.tar.xz
Convert all Intel i810 boards to CAR.
- Drop "select ROMCC" from the boards, as well as early_mtrr stuff. - Add "select CACHE_AS_RAM" to socket_PGA370/Kconfig, as well as the usual DCACHE_RAM_BASE and DCACHE_RAM_SIZE variables. - In socket_PGA370/Makefile.inc add: cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc - Other smaller related fixes. Abuild-tested and boot-tested on MSI MS-6178. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asus/mew-vm')
-rw-r--r--src/mainboard/asus/mew-vm/Kconfig1
-rw-r--r--src/mainboard/asus/mew-vm/romstage.c24
2 files changed, 5 insertions, 20 deletions
diff --git a/src/mainboard/asus/mew-vm/Kconfig b/src/mainboard/asus/mew-vm/Kconfig
index bc952dccbd..4e461923ad 100644
--- a/src/mainboard/asus/mew-vm/Kconfig
+++ b/src/mainboard/asus/mew-vm/Kconfig
@@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select NORTHBRIDGE_INTEL_I82810
select SOUTHBRIDGE_INTEL_I82801AX
select SUPERIO_SMSC_LPC47B272
- select ROMCC
select HAVE_OPTION_TABLE
select HAVE_PIRQ_TABLE
select UDELAY_TSC
diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c
index 30d6a87214..e4c551eb60 100644
--- a/src/mainboard/asus/mew-vm/romstage.c
+++ b/src/mainboard/asus/mew-vm/romstage.c
@@ -26,42 +26,28 @@
#include <arch/hlt.h>
#include <stdlib.h>
#include <console/console.h>
-#include "lib/ramtest.c"
#include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
#include "northbridge/intel/i82810/raminit.h"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
-
#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
#include "lib/debug.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "northbridge/intel/i82810/raminit.c"
#include "northbridge/intel/i82810/debug.c"
+#include <lib.h>
-static void main(unsigned long bist)
-{
- if (bist == 0)
- early_mtrr_init();
+#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1)
+void main(unsigned long bist)
+{
lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
-
enable_smbus();
-
- /* Halt if there was a built in self test failure. */
report_bist_failure(bist);
-
- /* dump_spd_registers(); */
-
+ dump_spd_registers();
sdram_set_registers();
sdram_set_spd_registers();
sdram_enable();
-
- /* Check RAM. */
- /* ram_check(0, 640 * 1024); */
}
-