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authorKeith Hui <buurin@gmail.com>2020-04-19 00:55:48 -0400
committerPatrick Georgi <pgeorgi@google.com>2020-05-11 09:33:23 +0000
commitedd38465a58d47b737f1e656a8055f64a3b0c421 (patch)
treec070c8409efa9728c132b6ad114f1aa628cd6c71 /src/mainboard/asus/p2b/Makefile.inc
parent75476ec3038497871741519c59ee2bfe3463e14b (diff)
downloadcoreboot-edd38465a58d47b737f1e656a8055f64a3b0c421.tar.xz
mainboard/asus/p3b-f: Reintroduce as variant of p2b
Fold this last ASUS 440BX board into the P2B family, while bringing in some changes: - Devicetree becomes overridetree. - Remove non-existent IR device and disable ACPI device on Super I/O to match OEM firmware. - Add SB GPO settings from OEM firmware to devicetree. This disables the SPD enabling magic this board needs. By moving the enabling part to bootblock the hacky enable_spd hook can be eliminated. - Initialize the serial port in bootblock, like the other boards. Boot tested on hardware. Change-Id: I65f2cb9d1bd4c82550de43889e3502526a46bd18 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41047 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/p2b/Makefile.inc')
-rw-r--r--src/mainboard/asus/p2b/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/asus/p2b/Makefile.inc b/src/mainboard/asus/p2b/Makefile.inc
index cc55c25a20..eb48944b6e 100644
--- a/src/mainboard/asus/p2b/Makefile.inc
+++ b/src/mainboard/asus/p2b/Makefile.inc
@@ -1,4 +1,5 @@
bootblock-y += bootblock.c
+romstage-$(CONFIG_BOARD_ASUS_P3B_F) += variants/$(VARIANT_DIR)/romstage.c
ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += variants/$(VARIANT_DIR)/irq_tables.c
ramstage-$(CONFIG_GENERATE_MP_TABLE) += variants/$(VARIANT_DIR)/mptable.c