Add acpi_get_sleep_type() to i82371eb and P2B _PTS/_WAK methods

Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP
Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2
uses the same acpi wakeup vector as S3.
Add _PTS/_WAK methods to turn off/on the CPU/case fans and blink
the power LED while sleeping.
acpi_get_sleep_type() is in a seperate file i82371eb_wakeup.c because
it is used in both romstage and ramstage after patch 3/3, whereas
i82371eb_early_pm.c is used only in romstage.
I used the name acpi_get_sleep_type instead of  acpi_is_wakeup_early
because I think acpi_is_wakeup_early is a bit misleading as a name since it
doesn't return a boolean value.

Other chipsets so far only ever set acpi_slp_type to 0 and 3, so the
added check for acpi_slp_type == 2 (resume from S2) should not
change behaviour of other boards:
northbridge/intel/i945/northbridge.c:256:extern u8 acpi_slp_type;
northbridge/intel/i945/northbridge.c:263: acpi_slp_type=0;
northbridge/intel/i945/northbridge.c:267: acpi_slp_type=3;
northbridge/intel/i945/northbridge.c:271: acpi_slp_type=0;
southbridge/intel/i82801gx/i82801gx_lpc.c:171:extern u8 acpi_slp_type;
southbridge/via/vt8237r/vt8237r_lpc.c:149:extern u8 acpi_slp_type;
southbridge/via/vt8237r/vt8237r_lpc.c:238:  acpi_slp_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
southbridge/via/vt8237r/vt8237r_lpc.c:239:  printk(BIOS_DEBUG, "SLP_TYP type was %x %x\n", tmp, acpi_slp_type);

Change-Id: I13feff0b8f49aa988e5467cdbef02981f0a6be8a
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/188
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 40 insertions, 16 deletions

diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl
index 5e6411ce1b..c5befa00b3 100644
--- a/src/mainboard/asus/p2b/dsdt.asl
+++ b/src/mainboard/asus/p2b/dsdt.asl
@@ -21,27 +21,51 @@
 
 DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE  ", "COREBOOT", 1)
 {
-	/* For now only define 2 power states:
-	 *  - S0 which is fully on
-	 *  - S5 which is soft off
-	 * Any others would involve declaring the wake up methods.
-	 */
-
-	/* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */
 	/*
-	000b / 0x0: soft off/suspend to disk (soff/std)			s5
-	001b / 0x1: suspend to ram (str)				s3
-	010b / 0x2: powered on suspend, context lost (poscl)		s1
-	011b / 0x3: powered on suspend, cpu context lost (posccl)	s2
-	100b / 0x4: powered on suspend, context maintained (pos)	s4
-	101b / 0x5: working (clock control)				s0
-	110b / 0x6: reserved
-	111b / 0x7: reserved
-	*/
+	 * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142
+	 *
+	 * 0: soft off/suspend to disk					S5
+	 * 1: suspend to ram						S3
+	 * 2: powered on suspend, context lost				S2
+	 *    Note: 'context lost' means the CPU restarts at the reset
+	 *          vector
+	 * 3: powered on suspend, CPU context lost			S1
+	 *    Note: Looks like 'CPU context lost' does _not_ mean the
+	 *          CPU restarts at the reset vector. Most likely only
+	 *          caches are lost, so both 0x3 and 0x4 map to acpi S1
+	 * 4: powered on suspend, context maintained			S1
+	 * 5: working (clock control)					S0
+	 * 6: reserved
+	 * 7: reserved
+	 */
 	Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 })
 	Name (\_S1, Package () { 0x03, 0x03, 0x00, 0x00 })
 	Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 })
 
+	OperationRegion (SIO1, SystemIO, Add(DEFAULT_PMBASE, GPO0), 2)
+	Field (SIO1, ByteAcc, NoLock, Preserve)
+	{
+		FANP,	1, /* CPU/case fan power */
+		Offset (0x01),
+		PLED,	1,
+	}
+
+	Method (\_PTS, 1, NotSerialized)
+	{
+		/* Disable fan, blink power led */
+		Store (Zero, FANP)
+		Store (Zero, PLED)
+	}
+
+	Method (\_WAK, 1, NotSerialized)
+	{
+		/* Re-enable fan, stop power led blinking */
+		Store (One, FANP)
+		Store (One, PLED)
+		/* wake OK */
+		Return(Package(0x02){0x00, 0x00})
+	}
+
 	/* Root of the bus hierarchy */
 	Scope (\_SB)
 	{