summaryrefslogtreecommitdiff
path: root/src/mainboard/asus/p3b-f/romstage.c
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-17 20:51:08 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-26 21:08:41 +0000
commitcd7a70f4879ff6e0f3e334ddf1031ccf0c0d31cf (patch)
treeb0438431df0943ab5f0fa9d80a99fc265130ac23 /src/mainboard/asus/p3b-f/romstage.c
parent16248e89ecf73a76e5d9e9e2de46146f7ffece88 (diff)
downloadcoreboot-cd7a70f4879ff6e0f3e334ddf1031ccf0c0d31cf.tar.xz
soc/intel: Use common romstage code
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/p3b-f/romstage.c')
-rw-r--r--src/mainboard/asus/p3b-f/romstage.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c
index cc5b764b01..8fc135d1c8 100644
--- a/src/mainboard/asus/p3b-f/romstage.c
+++ b/src/mainboard/asus/p3b-f/romstage.c
@@ -19,7 +19,7 @@
#include <console/console.h>
#include <southbridge/intel/i82371eb/i82371eb.h>
#include <northbridge/intel/i440bx/raminit.h>
-#include <cpu/intel/romstage.h>
+#include <arch/romstage.h>
#include <superio/winbond/common/winbond.h>
/* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */
#include <superio/winbond/w83977tf/w83977tf.h>