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authorElyes HAOUAS <ehaouas@noos.fr>2019-04-21 20:17:11 +0200
committerNico Huber <nico.h@gmx.de>2019-04-29 15:59:13 +0000
commitd07048a7f932aa779dc64d7c503df121c2a76f0b (patch)
tree6e05a847a7d2e81c82623c9d7bd9301b9a418940 /src/mainboard/asus/p5gc-mx
parent363b77177ea4bb7349dc418e355465b84d8accb5 (diff)
downloadcoreboot-d07048a7f932aa779dc64d7c503df121c2a76f0b.tar.xz
src/mb: Use system_reset()
Use already defined system_reset() function. Change-Id: I68ff4cffa2bfab6a15299795c3e1837fc9b85806 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32379 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/asus/p5gc-mx')
-rw-r--r--src/mainboard/asus/p5gc-mx/romstage.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index 6727f4ab88..beb276c7da 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -19,6 +19,7 @@
#include <stdint.h>
#include <arch/io.h>
+#include <cf9_reset.h>
#include <device/pnp_ops.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
@@ -214,8 +215,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (!s3resume && setup_sio_gpio(c_bsel)) {
printk(BIOS_DEBUG,
"Needs reset to configure CPU BSEL straps\n");
- outb(0xe, 0xcf9);
- halt();
+ full_reset();
}
/* Enable SPD ROMs and DDR-II DRAM */