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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-11 21:56:37 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-15 18:06:27 +0000 |
commit | 7843bd560e65b0a83e99b42bdd58dd6363656c56 (patch) | |
tree | 0d411ba99ae94da46d3fccaf09f1208fc812bb6f /src/mainboard/asus/p5qc/early_init.c | |
parent | c583920a748fb8bd7999142433ad08641b06283d (diff) | |
download | coreboot-7843bd560e65b0a83e99b42bdd58dd6363656c56.tar.xz |
nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK
There is some overlap between things done in bootblock
and romstage like setting BARs.
Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/p5qc/early_init.c')
-rw-r--r-- | src/mainboard/asus/p5qc/early_init.c | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/src/mainboard/asus/p5qc/early_init.c b/src/mainboard/asus/p5qc/early_init.c new file mode 100644 index 0000000000..cbc84ba101 --- /dev/null +++ b/src/mainboard/asus/p5qc/early_init.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <southbridge/intel/i82801jx/i82801jx.h> +#include <northbridge/intel/x4x/x4x.h> +#include <superio/winbond/w83667hg-a/w83667hg-a.h> +#include <superio/winbond/common/winbond.h> + +#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) + +void bootblock_mainboard_early_init(void) +{ + /* TODO? */ + RCBA32(RCBA_CG) = 0xbf7f001f; + RCBA32(0x3430) = 0x00000002; + RCBA32(0x3f00) = 0x00000038; + + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[1] = 0x51; + spd_map[2] = 0x52; + spd_map[3] = 0x53; +} |