mb/asus/p5qpl-am: Add mainboard

This mainboard has the BSEL straps hooked up to the SuperIO
similar to the ASUS P5GC-MX and might therefore require a restart.

Tested:
- FSB 800, 1067 and 1333MHz CPUs
- USB
- Ethernet
- Serial
- 2 DIMM slots
- SATA
- Libgfxinit (VGA)

TESTED with SeaBIOS (sercon disabled) and Linux 4.19.

Change-Id: Id845289081751ff8900e366592745f16d96f07c0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

1 files changed, 47 insertions, 0 deletions

diff --git a/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl b/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000000..ec461679f7
--- /dev/null
+++ b/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This is board specific information:
+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+	Return (Package() {
+		/* PCI1 SLOT 1 */
+		Package() { 0x0000ffff, 0, 0, 0x13},
+		Package() { 0x0000ffff, 1, 0, 0x10},
+		Package() { 0x0000ffff, 2, 0, 0x11},
+		Package() { 0x0000ffff, 3, 0, 0x12},
+
+		/* PCI1 SLOT 2 */
+		Package() { 0x0001ffff, 0, 0, 0x10},
+		Package() { 0x0001ffff, 1, 0, 0x11},
+		Package() { 0x0001ffff, 2, 0, 0x12},
+		Package() { 0x0001ffff, 3, 0, 0x13},
+	})
+} Else {
+	Return (Package() {
+		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},
+		Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0},
+		Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0},
+
+		Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+		Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+	})
+}