diff options
author | Angel Pons <th3fanbus@gmail.com> | 2018-06-13 14:13:15 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-14 12:13:13 +0000 |
commit | c69c8ddc2b62f008fafc85c66d993fd498417287 (patch) | |
tree | bdbcdbb900e818c9fcf4079d81b5a382720dd13c /src/mainboard/asus/p5qpl-am/romstage.c | |
parent | e124fa5a9d48d7248a1a1987805b9c1ac2bdbde8 (diff) | |
download | coreboot-c69c8ddc2b62f008fafc85c66d993fd498417287.tar.xz |
mb/asus/p5qpl-am: Add p5g41t-m_lx as a variant
This board has more or less the same as the p5qpl-am except for DDR3
memory and different colors on the ports. Tested with Arch Linux with
kernel 4.20.0-arch1-1-ARCH.
What is tested and works:
- 800/1066/1333 MHz CPUs and DDR3 sticks at 800/1066 MHz
Some bugs are still present in the DDR3 raminit code though.
- Ethernet
- Internal programmer with both coreboot and stock firmware.
- PCI and PCIe x1 slots
- All USB ports
- S3 resume
- SATA ports
- PEG
- Rear audio output
Change-Id: I92cd15a245c4f1d8f57b304c9c3a37ba29c35431
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/27089
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/p5qpl-am/romstage.c')
-rw-r--r-- | src/mainboard/asus/p5qpl-am/romstage.c | 77 |
1 files changed, 50 insertions, 27 deletions
diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 13e0364b3f..a541533398 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -51,12 +51,7 @@ static u8 msr_get_fsb(void) return fsbcfg; } -/* - * BSEL MCH straps are not hooked up to the CPU as usual but to the SIO - * BSEL0 -> not hooked up (such configs are not supported anyways) - * BSEL1 -> GPIO33 - * BSEL2 -> GPIO40 - */ +/* BSEL MCH straps are not hooked up to the CPU as usual but to the SIO */ static int setup_sio_gpio(void) { @@ -79,27 +74,55 @@ static int setup_sio_gpio(void) pnp_enter_ext_func_mode(GPIO_DEV); pnp_set_logical_device(GPIO_DEV); - reg = 0x92; - old_reg = pnp_read_config(GPIO_DEV, 0x2c); - pnp_write_config(GPIO_DEV, 0x2c, reg); - need_reset = (reg != old_reg); - - pnp_write_config(GPIO_DEV, 0x30, 0x06); - pnp_write_config(GPIO_DEV, 0xf0, 0xf3); /* GPIO3 direction */ - pnp_write_config(GPIO_DEV, 0xf4, 0x00); /* GPIO4 direction */ - - int gpio33 = (bsel & 2) >> 1; - int gpio40 = (bsel & 4) >> 2; - reg = (gpio33 << 3); - old_reg = pnp_read_config(GPIO_DEV, 0xf1); - pnp_write_config(GPIO_DEV, 0xf1, old_reg | reg); - need_reset += ((reg & 0x8) != (old_reg & 0x8)); - - reg = gpio40; - old_reg = pnp_read_config(GPIO_DEV, 0xf5); - pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg); - need_reset += ((reg & 0x1) != (old_reg & 0x1)); - + if (IS_ENABLED(CONFIG_BOARD_ASUS_P5QPL_AM)) { + /* + * P5QPL-AM: + * BSEL0 -> not hooked up (not supported anyways) + * BSEL1 -> GPIO33 + * BSEL2 -> GPIO40 + */ + reg = 0x92; + old_reg = pnp_read_config(GPIO_DEV, 0x2c); + pnp_write_config(GPIO_DEV, 0x2c, reg); + need_reset = (reg != old_reg); + + pnp_write_config(GPIO_DEV, 0x30, 0x06); + pnp_write_config(GPIO_DEV, 0xf0, 0xf3); /* GPIO3 direction */ + pnp_write_config(GPIO_DEV, 0xf4, 0x00); /* GPIO4 direction */ + + const int gpio33 = (bsel & 2) >> 1; + const int gpio40 = (bsel & 4) >> 2; + reg = (gpio33 << 3); + old_reg = pnp_read_config(GPIO_DEV, 0xf1); + pnp_write_config(GPIO_DEV, 0xf1, old_reg | reg); + need_reset += ((reg & 0x8) != (old_reg & 0x8)); + + reg = gpio40; + old_reg = pnp_read_config(GPIO_DEV, 0xf5); + pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg); + need_reset += ((reg & 0x1) != (old_reg & 0x1)); + } else { + /* + * P5G41T-M LX: + * BSEL0 -> not hooked up + * BSEL1 -> GPIO43 (inverted) + * BSEL2 -> GPIO44 + */ + reg = 0xf2; + old_reg = pnp_read_config(GPIO_DEV, 0x2c); + pnp_write_config(GPIO_DEV, 0x2c, reg); + need_reset = (reg != old_reg); + pnp_write_config(GPIO_DEV, 0x30, 0x05); + pnp_write_config(GPIO_DEV, 0xf6, 0x08); /* invert GPIO43 */ + pnp_write_config(GPIO_DEV, 0xf4, 0x00); /* GPIO4 direction */ + + const int gpio43 = (bsel & 2) >> 1; + const int gpio44 = (bsel & 4) >> 2; + reg = (gpio43 << 3) | (gpio44 << 4); + old_reg = pnp_read_config(GPIO_DEV, 0xf5); + pnp_write_config(GPIO_DEV, 0xf5, old_reg | reg); + need_reset += ((reg & 0x18) != (old_reg & 0x18)); + } pnp_exit_ext_func_mode(GPIO_DEV); return need_reset; |