diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-08 20:10:48 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-09 21:23:27 +0000 |
| commit | acabbce229e05f3a649bd3f97a4254acc7440966 (patch) | |
| tree | e57b0c787e6602611a1b6013c8d8296b23b3b3ec /src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb | |
| parent | 915d1eaeae417b5e0114da33efe87272e3adb6e5 (diff) | |
| download | coreboot-acabbce229e05f3a649bd3f97a4254acc7440966.tar.xz | |
mb/asus/p5qpl-am: Do not set BSEL GPIOs in devicetree
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are
set up in romstage, so it makes no sense to rewrite their values in
ramstage.
Tested, my Asus P5QPL-AM still boots.
Change-Id: Ic47f96d12420ebcc70ab5cea940c4c09620c03ca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb')
| -rw-r--r-- | src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb | 19 |
1 files changed, 6 insertions, 13 deletions
diff --git a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb index e84fd8a212..1305bff368 100644 --- a/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb +++ b/src/mainboard/asus/p5qpl-am/variants/p5qpl-am/overridetree.cb @@ -22,9 +22,6 @@ chip northbridge/intel/x4x # Northbridge chip superio/winbond/w83627dhg device pnp 2e.0 off end # Floppy device pnp 2e.1 on # Parallel port - # global - irq 0x2c = 0x92 - # parallel port io 0x60 = 0x378 irq 0x70 = 7 drq 0x74 = 3 @@ -40,16 +37,12 @@ chip northbridge/intel/x4x # Northbridge irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # SPI - device pnp 2e.7 on end # GPIO6 (all input) - device pnp 2e.8 off end # WDT0#, PLED - device pnp 2e.9 off end # GPIO2 - device pnp 2e.109 on # GPIO3 - irq 0xf0 = 0xf3 - end - device pnp 2e.209 on # GPIO4 - irq 0xf4 = 0x00 - end + device pnp 2e.6 off end # SPI + device pnp 2e.7 on end # GPIO6 (all input) + device pnp 2e.8 off end # WDT0#, PLED + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 on end # GPIO3 + device pnp 2e.209 on end # GPIO4 device pnp 2e.309 off end # GPIO5 device pnp 2e.a on # ACPI irq 0x70 = 0 |