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author | Angel Pons <th3fanbus@gmail.com> | 2021-04-02 22:49:27 +0200 |
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committer | Angel Pons <th3fanbus@gmail.com> | 2021-04-05 13:16:36 +0000 |
commit | f2e8660fa24b9e153967cc7e01486793806f9779 (patch) | |
tree | 0cbe6fd5eb9c7b3b833b939b9e7521408ec46903 /src/mainboard/asus/p8z77-v_lx2 | |
parent | e24f97c081f3e134362081913793d5adb90eddd5 (diff) | |
download | coreboot-f2e8660fa24b9e153967cc7e01486793806f9779.tar.xz |
sandybridge boards: Drop default `pci_mmio_size`
2 GiB is the default already.
Change-Id: I294460949659c97d4e19ad4e9d14f8c3566cca3f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52071
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/asus/p8z77-v_lx2')
-rw-r--r-- | src/mainboard/asus/p8z77-v_lx2/devicetree.cb | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb index 0fc6dc15b7..40f8e6db2b 100644 --- a/src/mainboard/asus/p8z77-v_lx2/devicetree.cb +++ b/src/mainboard/asus/p8z77-v_lx2/devicetree.cb @@ -10,7 +10,6 @@ chip northbridge/intel/sandybridge device lapic 0xacac off end end end - register "pci_mmio_size" = "2048" device domain 0 on subsystemid 0x1043 0x84ca inherit device pci 00.0 on end # Host bridge |