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| author | Timothy Pearson <tpearson@raptorengineering.com> | 2017-04-17 12:16:43 -0500 |
|---|---|---|
| committer | Timothy Pearson <tpearson@raptorengineering.com> | 2017-04-19 23:34:07 +0200 |
| commit | 2d35809530c5112276f713328bf964662488f793 (patch) | |
| tree | d9fc3542fe713269aec0208536c9abe36dcf1b21 /src/mainboard/asus | |
| parent | 992c7dba7e8513a63222b4d34b218864df20a609 (diff) | |
| download | coreboot-2d35809530c5112276f713328bf964662488f793.tar.xz | |
mb/asus/kgpe-d16: Enable TPM when selected in Kconfig
Issue TPM startup on romstage completion via common LPC TPM
code if the TPM was enabled in Kconfig.
Change-Id: Id886d6aeefa045fb979f128b1cf4c10fff243b24
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/19338
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/asus')
| -rw-r--r-- | src/mainboard/asus/kgpe-d16/romstage.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 7e8fb9725a..9459d6ceee 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 - 2016 Raptor Engineering, LLC + * Copyright (C) 2015 - 2017 Raptor Engineering, LLC * * Copyright (C) 2007 AMD * Written by Yinghai Lu <yinghailu@amd.com> for AMD. @@ -45,6 +45,7 @@ #include <cpu/amd/family_10h-family_15h/init_cpus.h> #include <arch/early_variables.h> #include <cbmem.h> +#include <tpm.h> #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" @@ -622,6 +623,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0); pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0); + if (IS_ENABLED(CONFIG_LPC_TPM)) + init_tpm(s3resume); + post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } |