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authorMyles Watson <mylesgw@gmail.com>2009-11-06 23:42:26 +0000
committerMyles Watson <mylesgw@gmail.com>2009-11-06 23:42:26 +0000
commitd27c08c2898d1d74765a7799628d1c18369fd671 (patch)
tree7ac357d2b44d833c6efe70d1e691c6611c521e8d /src/mainboard/asus
parent547d48ab01049a634dccb16d1847524d5ba93e33 (diff)
downloadcoreboot-d27c08c2898d1d74765a7799628d1c18369fd671.tar.xz
Remove drivers/pci/onboard. The only purpose was for option ROMs, which are
now handled more generically using CBFS. Simplify the option ROM code in device/pci_rom.c, since there are only two ways to get a ROM address now (CBFS and the device) and add an exception for qemu. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asus')
-rw-r--r--src/mainboard/asus/mew-vm/Config.lb4
-rw-r--r--src/mainboard/asus/mew-vm/devicetree.cb4
2 files changed, 0 insertions, 8 deletions
diff --git a/src/mainboard/asus/mew-vm/Config.lb b/src/mainboard/asus/mew-vm/Config.lb
index e27f2d12cf..3cd4db2e5f 100644
--- a/src/mainboard/asus/mew-vm/Config.lb
+++ b/src/mainboard/asus/mew-vm/Config.lb
@@ -97,18 +97,14 @@ chip northbridge/intel/i82810
device pci_domain 0 on
device pci 0.0 on end # Host bridge
device pci 1.0 on # Onboard Video
- #chip drivers/pci/onboard
# device pci 1.0 on end
- #end
end
chip southbridge/intel/i82801xx # Southbridge
register "ide0_enable" = "1"
register "ide1_enable" = "1"
device pci 1e.0 on # PCI Bridge
- #chip drivers/pci/onboard
# device pci 1.0 on end
- #end
end
device pci 1f.0 on # ISA/LPC? Bridge
chip superio/smsc/lpc47b272
diff --git a/src/mainboard/asus/mew-vm/devicetree.cb b/src/mainboard/asus/mew-vm/devicetree.cb
index 650aad1c42..0dc4b6f468 100644
--- a/src/mainboard/asus/mew-vm/devicetree.cb
+++ b/src/mainboard/asus/mew-vm/devicetree.cb
@@ -2,18 +2,14 @@ chip northbridge/intel/i82810
device pci_domain 0 on
device pci 0.0 on end # Host bridge
device pci 1.0 on # Onboard Video
- #chip drivers/pci/onboard
# device pci 1.0 on end
- #end
end
chip southbridge/intel/i82801xx # Southbridge
register "ide0_enable" = "1"
register "ide1_enable" = "1"
device pci 1e.0 on # PCI Bridge
- #chip drivers/pci/onboard
# device pci 1.0 on end
- #end
end
device pci 1f.0 on # ISA/LPC? Bridge
chip superio/smsc/lpc47b272