diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-06-09 11:59:00 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 09:32:34 +0000 |
commit | b0f1988f893bf5f581917816b11e810309955143 (patch) | |
tree | c4bcf6f1d9384b99cfcbfab4426de9f9f106e720 /src/mainboard/asus | |
parent | 68c851bcd702e7816cdb6e504f7386ec404ecf13 (diff) | |
download | coreboot-b0f1988f893bf5f581917816b11e810309955143.tar.xz |
src: Get rid of unneeded whitespace
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/asus')
-rw-r--r-- | src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl | 2 | ||||
-rw-r--r-- | src/mainboard/asus/kfsn4-dre/dsdt.asl | 2 | ||||
-rw-r--r-- | src/mainboard/asus/kfsn4-dre/resourcemap.c | 2 | ||||
-rw-r--r-- | src/mainboard/asus/kfsn4-dre/romstage.c | 8 | ||||
-rw-r--r-- | src/mainboard/asus/p3b-f/devicetree.cb | 114 |
5 files changed, 64 insertions, 64 deletions
diff --git a/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl b/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl index 0afb841435..bde6fb628d 100644 --- a/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl +++ b/src/mainboard/asus/kfsn4-dre/acpi/pm_ctrl.asl @@ -231,7 +231,7 @@ /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\_SB.SBRI, 0x13)) { - * Store(0,\_SB.PWDE) + * Store(0,\_SB.PWDE) *} */ diff --git a/src/mainboard/asus/kfsn4-dre/dsdt.asl b/src/mainboard/asus/kfsn4-dre/dsdt.asl index 2f1e86a14b..575715cf66 100644 --- a/src/mainboard/asus/kfsn4-dre/dsdt.asl +++ b/src/mainboard/asus/kfsn4-dre/dsdt.asl @@ -126,7 +126,7 @@ DefinitionBlock ( Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } - } /* End Scope GPE */ + } /* End Scope GPE */ /* Root of the bus hierarchy */ Scope (\_SB) diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c index cfbade68f2..f4e549b17f 100644 --- a/src/mainboard/asus/kfsn4-dre/resourcemap.c +++ b/src/mainboard/asus/kfsn4-dre/resourcemap.c @@ -226,7 +226,7 @@ static void setup_mb_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ -// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, +// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 56a6bdffd5..2809f0fe91 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -318,8 +318,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block */ if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) { - dump_spd_registers(&cpu[0]); - dump_smbus_registers(); + dump_spd_registers(&cpu[0]); + dump_smbus_registers(); } #endif @@ -344,8 +344,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Initialize GPIO */ /* Access SuperIO GPI03 logical device */ uint16_t port = GPIO3_DEV >> 8; - outb(0x87, port); - outb(0x87, port); + outb(0x87, port); + outb(0x87, port); pnp_set_logical_device(GPIO3_DEV); /* Set GP37 (power LED) to output */ pnp_write_config(GPIO3_DEV, 0xf0, 0x7f); diff --git a/src/mainboard/asus/p3b-f/devicetree.cb b/src/mainboard/asus/p3b-f/devicetree.cb index 5bee5ae96a..bc9ad17c93 100644 --- a/src/mainboard/asus/p3b-f/devicetree.cb +++ b/src/mainboard/asus/p3b-f/devicetree.cb @@ -1,59 +1,59 @@ chip northbridge/intel/i440bx # Northbridge - device cpu_cluster 0 on # APIC cluster - chip cpu/intel/slot_1 # CPU - device lapic 0 on end # APIC - end - end - device domain 0 on # PCI domain - device pci 0.0 on end # Host bridge - device pci 1.0 on end # PCI/AGP bridge - chip southbridge/intel/i82371eb # Southbridge - device pci 4.0 on # ISA bridge - chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) - device pnp 3f0.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 3f0.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 3f0.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 3f0.3 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 3f0.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 3f0.6 on # Consumer IR - end - device pnp 3f0.7 on # GPIO 1 - end - device pnp 3f0.8 on # GPIO 2 - end - device pnp 3f0.a on # ACPI - end - end - end - device pci 4.1 on end # IDE - device pci 4.2 on end # USB - device pci 4.3 on end # ACPI - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "ide_legacy_enable" = "1" - # Enable UDMA/33 for higher speed if your IDE device(s) support it. - register "ide0_drive0_udma33_enable" = "0" - register "ide0_drive1_udma33_enable" = "0" - register "ide1_drive0_udma33_enable" = "0" - register "ide1_drive1_udma33_enable" = "0" - end - end + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/slot_1 # CPU + device lapic 0 on end # APIC + end + end + device domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 4.0 on # ISA bridge + chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 3f0.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.3 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.6 on # Consumer IR + end + device pnp 3f0.7 on # GPIO 1 + end + device pnp 3f0.8 on # GPIO 2 + end + device pnp 3f0.a on # ACPI + end + end + end + device pci 4.1 on end # IDE + device pci 4.2 on end # USB + device pci 4.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + end end |