Clean up #ifs

Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +

Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +

Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +

Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +

(and some manual changes to fix false positives)

Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>

24 files changed, 34 insertions, 34 deletions

diff --git a/src/mainboard/asus/a8n_e/get_bus_conf.c b/src/mainboard/asus/a8n_e/get_bus_conf.c
index 75741fddc5..ce1448d381 100644
--- a/src/mainboard/asus/a8n_e/get_bus_conf.c
+++ b/src/mainboard/asus/a8n_e/get_bus_conf.c
@@ -27,7 +27,7 @@
 #include <string.h>
 #include <stdint.h>
 #include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
 #include <cpu/amd/multicore.h>
 #endif
 #include <cpu/amd/amdk8_sysconf.h>
@@ -114,7 +114,7 @@ void get_bus_conf(void)
 		}
 	}
 
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	apicid_base = get_apicid_base(3);
 #else
 	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index b3e85b7d83..fcbe86d0a6 100644
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -121,7 +121,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	needs_reset = setup_coherent_ht_domain();
 
 	wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	/* It is said that we should start core1 after all core0 launched. */
 	start_other_cores();
 	wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index 47a0e656f1..53a1fbc6b8 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -190,7 +190,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	print_info("now booting... Core0 started\n");
 
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	/* It is said that we should start core1 after all core0 launched. */
 	start_other_cores();
 	wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 41934523c0..7539a80e17 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -192,7 +192,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	print_info("now booting... Core0 started\n");
 
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	/* It is said that we should start core1 after all core0 launched. */
 	start_other_cores();
 	wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index f24c4d40c8..82b0636b01 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -163,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	print_info("now booting... Core0 started\n");
 
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	/* It is said that we should start core1 after all core0 launched. */
 	start_other_cores();
 	wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/asus/m2n-e/get_bus_conf.c b/src/mainboard/asus/m2n-e/get_bus_conf.c
index a39ac22d7e..031b67388a 100644
--- a/src/mainboard/asus/m2n-e/get_bus_conf.c
+++ b/src/mainboard/asus/m2n-e/get_bus_conf.c
@@ -24,7 +24,7 @@
 #include <device/pci_ids.h>
 #include <string.h>
 #include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 #include <cpu/amd/multicore.h>
 #endif
 #include <cpu/amd/amdk8_sysconf.h>
@@ -112,7 +112,7 @@ void get_bus_conf(void)
 			bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
 	}
 
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
 	apicid_base = get_apicid_base(1);
 #else
 	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
index e820a79244..21ca89e6fd 100644
--- a/src/mainboard/asus/m2n-e/romstage.c
+++ b/src/mainboard/asus/m2n-e/romstage.c
@@ -20,7 +20,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
@@ -134,7 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	setup_coherent_ht_domain(); /* Routing table and start other core0. */
 	wait_all_core0_started();
 
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
 	/*
 	 * It is said that we should start core1 after all core0 launched
 	 * becase optimize_link_coherent_ht is moved out from
diff --git a/src/mainboard/asus/m2v-mx_se/mainboard.c b/src/mainboard/asus/m2v-mx_se/mainboard.c
index 614af3908e..c936fa9042 100644
--- a/src/mainboard/asus/m2v-mx_se/mainboard.c
+++ b/src/mainboard/asus/m2v-mx_se/mainboard.c
@@ -30,7 +30,7 @@ uint64_t uma_memory_base, uma_memory_size;
 
 int add_mainboard_resources(struct lb_memory *mem)
 {
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		uma_memory_base, uma_memory_size);
 #endif
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index 9825e2bcfb..ac88f6a532 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -24,7 +24,7 @@
 
 unsigned int get_sbdn(unsigned bus);
 
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
@@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_INFO, "now booting... All core 0 started\n");
 
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	/* It is said that we should start core1 after all core0 launched. */
 	start_other_cores();
 	wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index 53a3fc38d2..367ef3b338 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -24,7 +24,7 @@
 
 unsigned int get_sbdn(unsigned bus);
 
-#if CONFIG_K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
@@ -256,7 +256,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	printk(BIOS_INFO, "now booting... All core 0 started\n");
 
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	/* It is said that we should start core1 after all core0 launched. */
 	start_other_cores();
 	wait_all_other_cores_started(bsp_apicid);
diff --git a/src/mainboard/asus/m4a78-em/get_bus_conf.c b/src/mainboard/asus/m4a78-em/get_bus_conf.c
index b169775456..563a87efd5 100644
--- a/src/mainboard/asus/m4a78-em/get_bus_conf.c
+++ b/src/mainboard/asus/m4a78-em/get_bus_conf.c
@@ -23,7 +23,7 @@
 #include <string.h>
 #include <stdint.h>
 #include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 #include <cpu/amd/multicore.h>
 #endif
 
@@ -107,7 +107,7 @@ void get_bus_conf(void)
 	}
 
 	/* I/O APICs:   APIC ID Version State   Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	apicid_base = get_apicid_base(1);
 #else
 	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c
index 4854208b9d..10ecb64e36 100644
--- a/src/mainboard/asus/m4a78-em/mainboard.c
+++ b/src/mainboard/asus/m4a78-em/mainboard.c
@@ -125,7 +125,7 @@ static void m4a78em_enable(device_t dev)
 {
 	printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
 
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	msr_t msr, msr2;
 
 	/* TOP_MEM: the top of DRAM below 4G */
diff --git a/src/mainboard/asus/m4a78-em/mptable.c b/src/mainboard/asus/m4a78-em/mptable.c
index 4a276fb0c3..d7951cf8be 100644
--- a/src/mainboard/asus/m4a78-em/mptable.c
+++ b/src/mainboard/asus/m4a78-em/mptable.c
@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
 #define PCI_INT(bus, dev, fn, pin) \
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
 #else
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index a96592d20c..50bbfcac06 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -148,7 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 */
 	wait_all_core0_started();
 
- #if CONFIG_LOGICAL_CPUS==1
+ #if CONFIG_LOGICAL_CPUS
 	/* Core0 on each node is configured. Now setup any additional cores. */
 	printk(BIOS_DEBUG, "start_other_cores()\n");
 	start_other_cores();
diff --git a/src/mainboard/asus/m4a785-m/get_bus_conf.c b/src/mainboard/asus/m4a785-m/get_bus_conf.c
index b169775456..563a87efd5 100644
--- a/src/mainboard/asus/m4a785-m/get_bus_conf.c
+++ b/src/mainboard/asus/m4a785-m/get_bus_conf.c
@@ -23,7 +23,7 @@
 #include <string.h>
 #include <stdint.h>
 #include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 #include <cpu/amd/multicore.h>
 #endif
 
@@ -107,7 +107,7 @@ void get_bus_conf(void)
 	}
 
 	/* I/O APICs:   APIC ID Version State   Address */
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	apicid_base = get_apicid_base(1);
 #else
 	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c
index d152f71d7d..3b681434c0 100644
--- a/src/mainboard/asus/m4a785-m/mainboard.c
+++ b/src/mainboard/asus/m4a785-m/mainboard.c
@@ -197,7 +197,7 @@ static void m4a785m_enable(device_t dev)
 {
 	printk(BIOS_INFO, "Mainboard enable. dev=0x%p\n", dev);
 
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	msr_t msr, msr2;
 
 	/* TOP_MEM: the top of DRAM below 4G */
diff --git a/src/mainboard/asus/m4a785-m/mptable.c b/src/mainboard/asus/m4a785-m/mptable.c
index 4a276fb0c3..d7951cf8be 100644
--- a/src/mainboard/asus/m4a785-m/mptable.c
+++ b/src/mainboard/asus/m4a785-m/mptable.c
@@ -100,7 +100,7 @@ static void *smp_write_config_table(void *v)
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
 #define PCI_INT(bus, dev, fn, pin) \
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin))
 #else
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 870af70f65..f0be2f7793 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -148,7 +148,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 */
 	wait_all_core0_started();
 
- #if CONFIG_LOGICAL_CPUS==1
+ #if CONFIG_LOGICAL_CPUS
 	/* Core0 on each node is configured. Now setup any additional cores. */
 	printk(BIOS_DEBUG, "start_other_cores()\n");
 	start_other_cores();
diff --git a/src/mainboard/asus/m5a88-v/acpi_tables.c b/src/mainboard/asus/m5a88-v/acpi_tables.c
index 9642bb4e19..fa93842dfc 100644
--- a/src/mainboard/asus/m5a88-v/acpi_tables.c
+++ b/src/mainboard/asus/m5a88-v/acpi_tables.c
@@ -236,7 +236,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_create_facs(facs);
 
 	/* FDAT */
-#if CONFIG_BOARD_HAS_FADT == 1
+#if CONFIG_BOARD_HAS_FADT
 	current = ALIGN(current, 8);
 	printk(BIOS_DEBUG, "ACPI:    * FADT at %lx\n", current);
 	fadt = (acpi_fadt_t *) current;
diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c
index 5c21e09d53..fcf0bd9100 100644
--- a/src/mainboard/asus/m5a88-v/get_bus_conf.c
+++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c
@@ -23,7 +23,7 @@
 #include <string.h>
 #include <stdint.h>
 #include <stdlib.h>
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 #include <cpu/amd/multicore.h>
 #endif
 #include <cpu/amd/amdfam10_sysconf.h>
@@ -141,7 +141,7 @@ void get_bus_conf(void)
 
 	/* I/O APICs:   APIC ID Version State   Address */
 	bus_isa = 10;
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	apicid_base = get_apicid_base(1);
 #else
 	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c
index 7fa4ee7404..38b964839a 100644
--- a/src/mainboard/asus/m5a88-v/mainboard.c
+++ b/src/mainboard/asus/m5a88-v/mainboard.c
@@ -81,7 +81,7 @@ static void m5a88pm_v_enable(device_t dev)
 
 	printk(BIOS_INFO, "Mainboard ASUS M5A88-V Enable. dev=0x%p\n", dev);
 
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	msr_t msr, msr2;
 
 	/* TOP_MEM: the top of DRAM below 4G */
@@ -130,7 +130,7 @@ int add_mainboard_resources(struct lb_memory *mem)
 	/* UMA is removed from system memory in the northbridge code, but
 	 * in some circumstances we want the memory mentioned as reserved.
 	 */
-#if (CONFIG_GFXUMA == 1)
+#if CONFIG_GFXUMA
 	printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
 		    uma_memory_base, uma_memory_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
diff --git a/src/mainboard/asus/m5a88-v/mptable.c b/src/mainboard/asus/m5a88-v/mptable.c
index ac8ed5e45b..7daa5d1312 100644
--- a/src/mainboard/asus/m5a88-v/mptable.c
+++ b/src/mainboard/asus/m5a88-v/mptable.c
@@ -79,7 +79,7 @@ static void *smp_write_config_table(void *v)
 	/* PCI interrupts are level triggered, and are
 	 * associated with a specific bus/device/function tuple.
 	 */
-#if CONFIG_GENERATE_ACPI_TABLES == 0
+#if !CONFIG_GENERATE_ACPI_TABLES
 #define PCI_INT(bus, dev, fn, pin) \
         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb800, (pin))
 #else
diff --git a/src/mainboard/asus/m5a88-v/platform_cfg.h b/src/mainboard/asus/m5a88-v/platform_cfg.h
index 43573f19a5..00f9695440 100644
--- a/src/mainboard/asus/m5a88-v/platform_cfg.h
+++ b/src/mainboard/asus/m5a88-v/platform_cfg.h
@@ -36,7 +36,7 @@
  * bigger than 1M you have to set the ROM size outside CIMx module and
  * before AGESA module get call.
  */
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1
+#if CONFIG_COREBOOT_ROMSIZE_KB_1024
   #define BIOS_SIZE BIOS_SIZE_1M
 #elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1
   #define BIOS_SIZE BIOS_SIZE_2M
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 9d8e08ac66..22d87b37bc 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -159,7 +159,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 */
 	wait_all_core0_started();
 
-#if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS
 	/* Core0 on each node is configured. Now setup any additional cores. */
 	printk(BIOS_DEBUG, "start_other_cores()\n");
 	start_other_cores();
@@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	/* run _early_setup before soft-reset. */
 	rs780_early_setup();
 
-#if CONFIG_SET_FIDVID == 1
+#if CONFIG_SET_FIDVID
 	msr = rdmsr(0xc0010071);
 	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
 	post_code(0x39);