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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-05-06 23:53:09 +1000
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-05-13 10:03:38 +0200
commite61dd0f7a2be83ce5ba87d74f7384111576ffd49 (patch)
treea9f2c51500bbd8702cf039c8e620653d25c4b4d8 /src/mainboard/asus
parent216a619a74d61f66e3d3e1d668028d11a8868b4d (diff)
downloadcoreboot-e61dd0f7a2be83ce5ba87d74f7384111576ffd49.tar.xz
southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridge
We should configure i8254/i8259 down in to the southbridge rather than romstage of every AGESA/CIMx board much like Intel boards do. Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5669 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/asus')
-rw-r--r--src/mainboard/asus/f2a85-m/romstage.c11
1 files changed, 0 insertions, 11 deletions
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index 487f0684a1..ffd91bfd6e 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -38,9 +38,6 @@
#include <string.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8712f/it8712f.h>
-/* TODO: remove .c includes */
-#include <drivers/pc80/i8254.c>
-#include <drivers/pc80/i8259.c>
#define MMIO_NON_POSTED_START 0xfed00000
#define MMIO_NON_POSTED_END 0xfedfffff
@@ -201,14 +198,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
#endif
- /* Initialize i8259 pic */
- post_code(0x41);
- setup_i8259 ();
-
- /* Initialize i8254 timers */
- post_code(0x42);
- setup_i8254 ();
-
post_code(0x50);
copy_and_run();