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| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-14 20:10:11 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-14 20:10:11 +0000 |
| commit | 0675d5c34f90d0b2a3864d0f30461dfe696374f0 (patch) | |
| tree | 148ca976cda1859cf53fb9a7a7ebb9dc44eb2130 /src/mainboard/asus | |
| parent | 727edb0b320e46acc8ab272fdec87e6444203bfe (diff) | |
| download | coreboot-0675d5c34f90d0b2a3864d0f30461dfe696374f0.tar.xz | |
CK804/MCP55 devicetree.cb cosmetic and indentation fixes.
Add a few more comments for the entries, and also change the devicetree.cb
files to the more compact and better readable variant with indentation level
of 2 spaces (instead of random mix of tabs and spaces).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6071 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asus')
| -rw-r--r-- | src/mainboard/asus/a8n_e/devicetree.cb | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/src/mainboard/asus/a8n_e/devicetree.cb b/src/mainboard/asus/a8n_e/devicetree.cb index c5a4c886c0..ca2ebf9ed0 100644 --- a/src/mainboard/asus/a8n_e/devicetree.cb +++ b/src/mainboard/asus/a8n_e/devicetree.cb @@ -1,14 +1,13 @@ chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # Socket 939 CPU - device lapic 0 on end # APIC + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_939 # CPU socket + device lapic 0 on end # Local APIC of the CPU end end device pci_domain 0 on # PCI domain - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 chip southbridge/nvidia/ck804 # Southbridge device pci 0.0 on end # HT device pci 1.0 on # LPC @@ -62,7 +61,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex io 0xc8 = 0x0000 io 0xca = 0x0500 end - device pnp 2e.8 on # Midi port + device pnp 2e.8 on # MIDI port io 0x60 = 0x300 irq 0x70 = 10 end @@ -76,28 +75,28 @@ chip northbridge/amd/amdk8/root_complex # Root complex end end device pci 1.1 on # SM 0 - # chip drivers/generic/generic #dimm 0-0-0 + # chip drivers/generic/generic # DIMM 0-0-0 # device i2c 50 on end # end - # chip drivers/generic/generic #dimm 0-0-1 + # chip drivers/generic/generic # DIMM 0-0-1 # device i2c 51 on end # end - # chip drivers/generic/generic #dimm 0-1-0 + # chip drivers/generic/generic # DIMM 0-1-0 # device i2c 52 on end # end - # chip drivers/generic/generic #dimm 0-1-1 + # chip drivers/generic/generic # DIMM 0-1-1 # device i2c 53 on end # end - # chip drivers/generic/generic #dimm 1-0-0 + # chip drivers/generic/generic # DIMM 1-0-0 # device i2c 54 on end # end - # chip drivers/generic/generic #dimm 1-0-1 + # chip drivers/generic/generic # DIMM 1-0-1 # device i2c 55 on end # end - # chip drivers/generic/generic #dimm 1-1-0 + # chip drivers/generic/generic # DIMM 1-1-0 # device i2c 56 on end # end - # chip drivers/generic/generic #dimm 1-1-1 + # chip drivers/generic/generic # DIMM 1-1-1 # device i2c 57 on end # end end @@ -118,6 +117,7 @@ chip northbridge/amd/amdk8/root_complex # Root complex register "ide1_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" + # TODO # register "mac_eeprom_smbus" = "3" # register "mac_eeprom_addr" = "0x51" end |