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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-11-05 13:16:55 -0600
committerMartin Roth <martinroth@google.com>2015-12-15 16:43:09 +0100
commitecd4cfcb8695988d82069df4509b56e39794379e (patch)
tree23fa5332abdbab0e7a41b0038635bad780e68ed7 /src/mainboard/asus
parent44d53428352ff5d6c8941160429735b5465add5f (diff)
downloadcoreboot-ecd4cfcb8695988d82069df4509b56e39794379e.tar.xz
mainboard/asus/kgpe-d16: Enable romstage spinlocks
Change-Id: Iac1adbeacdcded7faff2443b78a491cbb8a90fe8 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12628 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/asus')
-rw-r--r--src/mainboard/asus/kgpe-d16/Kconfig1
-rw-r--r--src/mainboard/asus/kgpe-d16/romstage.c20
2 files changed, 16 insertions, 5 deletions
diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig
index c4f3962f63..67b43ca4d5 100644
--- a/src/mainboard/asus/kgpe-d16/Kconfig
+++ b/src/mainboard/asus/kgpe-d16/Kconfig
@@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_AMD_SUBTYPE_SP5100
select SUPERIO_NUVOTON_NCT5572D
select PARALLEL_CPU_INIT
+ select HAVE_ROMSTAGE_CONSOLE_SPINLOCK
select HAVE_HARD_RESET
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index df76ab4e55..13eacd25b5 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -312,6 +312,18 @@ static void execute_memory_test(void)
}
#endif
+static spinlock_t printk_spinlock CAR_GLOBAL;
+
+spinlock_t* romstage_console_lock(void)
+{
+ return car_get_var_ptr(&printk_spinlock);
+}
+
+void initialize_romstage_console_lock(void)
+{
+ car_get_var(printk_spinlock) = SPIN_LOCK_UNLOCKED;
+}
+
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
uint32_t esp;
@@ -338,6 +350,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
+ /* Initialize the printk spinlock */
+ initialize_romstage_console_lock();
+
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
set_bsp_node_CHtExtNodeCfgEn();
@@ -407,11 +422,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x36);
/* Wait for all the APs core0 started by finalize_node_setup. */
- /* FIXME: A bunch of cores are going to start output to serial at once.
- * It would be nice to fix up prink spinlocks for ROM XIP mode.
- * I think it could be done by putting the spinlock flag in the cache
- * of the BSP located right after sysinfo.
- */
wait_all_core0_started();
/* run _early_setup before soft-reset. */