diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-04-22 13:18:09 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-04-22 13:18:09 +0000 |
| commit | 64d3baf9829baf9285c94cae0406ee0f428c04c0 (patch) | |
| tree | b80df0a87ad9bfecd2e6b2913eb5ff80535aee04 /src/mainboard/asus | |
| parent | 4292685f5adbe45bb5b23f32c3b6aaed04187f48 (diff) | |
| download | coreboot-64d3baf9829baf9285c94cae0406ee0f428c04c0.tar.xz | |
zero warnings days...
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asus')
| -rw-r--r-- | src/mainboard/asus/m2v-mx_se/romstage.c | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 3ece7aa22b..04a5206437 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -57,7 +57,6 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -83,10 +82,11 @@ static void activate_spd_rom(const struct mem_controller *ctrl) { } -#define K8_4RANK_DIMM_SUPPORT 1 - +// defines S3_NVRAM_EARLY: #include "southbridge/via/k8t890/k8t890_early_car.c" +#define K8_4RANK_DIMM_SUPPORT 1 + #include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -164,7 +164,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); enable_rom_decode(); - print_info("now booting... real_main\n"); + printk(BIOS_INFO, "now booting... \n"); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); @@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); wait_all_core0_started(); - print_info("now booting... Core0 started\n"); + printk(BIOS_INFO, "now booting... All core 0 started\n"); #if CONFIG_LOGICAL_CPUS==1 /* It is said that we should start core1 after all core0 launched. */ @@ -196,12 +196,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) vt8237_early_spi_init(); if (needs_reset) { - print_debug_hex8(needs_reset); - - print_debug("Xht reset -\n"); + printk(BIOS_DEBUG, "ht reset -\n"); soft_reset(); - print_debug("NO reset\n"); - + printk(BIOS_DEBUG, "FAILED!\n"); } /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ |