Various cosmetic and coding style fixes for ASUS A8V-E SE (trivial).

No functional changes, only cosmetics. This is compile-tested.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3128 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

9 files changed, 522 insertions, 795 deletions

diff --git a/src/mainboard/asus/a8v-e_se/Config.lb b/src/mainboard/asus/a8v-e_se/Config.lb
index e8841adf6e..aa5ca70703 100644
--- a/src/mainboard/asus/a8v-e_se/Config.lb
+++ b/src/mainboard/asus/a8v-e_se/Config.lb
@@ -2,8 +2,7 @@
 ## This file is part of the coreboot project.
 ## 
 ## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
+## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
 ## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
 ## 
 ## This program is free software; you can redistribute it and/or modify
@@ -21,260 +20,195 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ## 
 
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-    if USE_FALLBACK_IMAGE
-	default ROM_SECTION_SIZE   = FALLBACK_SIZE
-	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-    else
-	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-	default ROM_SECTION_OFFSET = 0
-    end
+if USE_FALLBACK_IMAGE
+  default ROM_SECTION_SIZE   = FALLBACK_SIZE
+  default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+  default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+  default ROM_SECTION_OFFSET = 0
+end
 
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default PAYLOAD_SIZE             = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+default CONFIG_ROM_PAYLOAD       = 1
+default _ROMBASE     = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
+default XIP_ROM_SIZE = 65536
+default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
 
 arch i386 end 
 
-##
-## Build the objects we have code for in this directory.
-##
-
 driver mainboard.o
-
 if HAVE_ACPI_TABLES
-        object acpi_tables.o
-        object fadt.o
-	makerule dsdt.c
-		depends "$(MAINBOARD)/dsdt.asl"
-		action  "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.asl"
-		action  "mv dsdt.hex dsdt.c"
-	end
-        object ./dsdt.o
+  object acpi_tables.o
+  object fadt.o
+  makerule dsdt.c
+    depends "$(MAINBOARD)/dsdt.asl"
+    action  "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.asl"
+    action  "mv dsdt.hex dsdt.c"
+  end
+  object ./dsdt.o
 end
-
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-#object reset.o
-if USE_DCACHE_RAM
-
-	if CONFIG_USE_INIT	
-		makerule ./cache_as_ram_auto.o
-		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        		action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
-		end
-	else
-		makerule ./cache_as_ram_auto.inc
-        		depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
-		        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
-        		action "perl -e 's/.text/.section .rom.text/g' -pi $@"
-		end
-	end
+# object reset.o
 
+if USE_DCACHE_RAM
+  if CONFIG_USE_INIT
+    makerule ./cache_as_ram_auto.o
+      depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+      action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+    end
+  else
+    makerule ./cache_as_ram_auto.inc
+      depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+      action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+      action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+      action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+    end
+  end
 end
 
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-
 if USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-	mainboardinit southbridge/via/k8t890/romstrap.inc
-	ldscript /southbridge/via/k8t890/romstrap.lds
-
+  mainboardinit cpu/x86/16bit/entry16.inc
+  ldscript /cpu/x86/16bit/entry16.lds
+  mainboardinit southbridge/via/k8t890/romstrap.inc
+  ldscript /southbridge/via/k8t890/romstrap.lds
 end
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
 if USE_DCACHE_RAM
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/amd/car/cache_as_ram.lds
-        end
+  if CONFIG_USE_INIT
+    ldscript /cpu/x86/32bit/entry32.lds
+  end
+  if CONFIG_USE_INIT
+    ldscript /cpu/amd/car/cache_as_ram.lds
+  end
 end
 
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-
-if USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
+if USE_FALLBACK_IMAGE
+  mainboardinit cpu/x86/16bit/reset16.inc
+  ldscript /cpu/x86/16bit/reset16.lds
 else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
+  mainboardinit cpu/x86/32bit/reset32.inc
+  ldscript /cpu/x86/32bit/reset32.lds
 end
 
 if USE_DCACHE_RAM
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
+  mainboardinit cpu/amd/car/cache_as_ram.inc
 end
 
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-
 if USE_FALLBACK_IMAGE
-	if USE_DCACHE_RAM
-		ldscript /arch/i386/lib/failover.lds
-	end
+  if USE_DCACHE_RAM
+    ldscript /arch/i386/lib/failover.lds
+  end
 end
 
-
-##
-## Setup RAM
-##
 if USE_DCACHE_RAM
-
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
+  if CONFIG_USE_INIT
+    initobject cache_as_ram_auto.o
+  else
+    mainboardinit ./cache_as_ram_auto.inc
+  end
 end
 
-##
-## Include the secondary Configuration files 
-##
 if CONFIG_CHIP_NAME
-	config chip.h
+  config chip.h
 end
 
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_939
-                        device apic 0 on end
-                end
+chip northbridge/amd/amdk8/root_complex		# Root complex
+  device apic_cluster 0 on			# APIC cluster
+    chip cpu/amd/socket_939			# CPU
+      device apic 0 on end			# APIC
+    end
+  end
+  device pci_domain 0 on			# PCI domain
+    chip northbridge/amd/amdk8			# mc0
+      device pci 18.0 on			# Northbridge
+        # Devices on link 0, link 0 == LDT 0
+        chip southbridge/via/vt8237r		# Southbridge
+          register "ide0_enable" = "1"		# Enable IDE channel 0
+          register "ide1_enable" = "1"		# Enable IDE channel 1
+          register "ide0_80pin_cable" = "1"	# 80pin cable on IDE channel 0
+          register "ide1_80pin_cable" = "1"	# 80pin cable on IDE channel 1
+          register "fn_ctrl_lo" = "0"		# Enable SB functions
+          register "fn_ctrl_hi" = "0xad"	# Enable SB functions
+          device pci 0.0 on end			# HT
+          device pci f.1 on end			# IDE
+          device pci 11.0 on			# LPC
+            chip drivers/generic/generic	# DIMM 0-0-0
+              device i2c 50 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-0-1
+              device i2c 51 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-1-0
+              device i2c 52 on end
+            end
+            chip drivers/generic/generic	# DIMM 0-1-1
+              device i2c 53 on end
+            end
+            chip superio/winbond/w83627ehg	# Super I/O
+              device pnp 2e.0 on		# Floppy
+                io 0x60 = 0x3f0
+                irq 0x70 = 6
+                drq 0x74 = 2
+              end
+              device pnp 2e.1 on		# Parallel port
+                io 0x60 = 0x378
+                irq 0x70 = 7
+                drq 0x74 = 3
+              end
+              device pnp 2e.2 on		# Com1
+                io 0x60 = 0x3f8
+                irq 0x70 = 4
+              end
+              device pnp 2e.3 off		# Com2 (N/A on this board)
+                io 0x60 = 0x2f8
+                irq 0x70 = 3
+              end
+              device pnp 2e.5 off		# PS/2 keyboard (off)
+              end
+              device pnp 2e.106 off		# Serial flash
+                io 0x60 = 0x100
+              end
+              device pnp 2e.007 off		# GPIO 1
+              end
+              device pnp 2e.107 on		# Game port
+                io 0x60 = 0x201
+              end
+              device pnp 2e.207 on		# MIDI
+                io 0x62 = 0x330
+                irq 0x70 = 0xa
+              end
+              device pnp 2e.307 off		# GPIO 6
+              end
+              device pnp 2e.8 off		# WDTO_PLED
+              end
+              device pnp 2e.009 on		# GPIO 2 on LDN 9 is in sio_setup
+              end
+              device pnp 2e.109 off		# GPIO 3
+              end
+              device pnp 2e.209 off		# GPIO 4
+              end
+              device pnp 2e.309 on		# GPIO5
+              end
+              device pnp 2e.a off		# ACPI
+              end
+              device pnp 2e.b on		# Hardware monitor
+                io 0x60 = 0x290
+                irq 0x70 = 0
+              end
+            end
+          end
+          device pci 12.0 off end		# VIA LAN (off, other chip used)
         end
-
-       device pci_domain 0 on
-               chip northbridge/amd/amdk8 #mc0
-                       device pci 18.0 on #  northbridge
-                               #  devices on link 0, link 0 == LDT 0
-                               chip southbridge/via/vt8237r
-					#both IDE channels
-					register "ide0_enable" = "1"
-					register "ide1_enable" = "1"
-					#both cables are 80pin
-					register "ide0_80pin_cable" = "1"
-					register "ide1_80pin_cable" = "1"
-					#enables the functions of SB
-					register "fn_ctrl_lo" = "0"
-					register "fn_ctrl_hi" = "0xad"
-					
-                                       device pci 0.0 on end   # HT
-                                       device pci f.1 on end   # IDE
-                                       device pci 11.0 on # LPC
-                                                chip drivers/generic/generic #dimm 0-0-0
-                                                        device i2c 50 on end  
-                                                end              
-                                                chip drivers/generic/generic #dimm 0-0-1
-                                                        device i2c 51 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 0-1-0
-                                                        device i2c 52 on end
-                                                end             
-                                                chip drivers/generic/generic #dimm 0-1-1
-                                                        device i2c 53 on end
-                                                end              
-
-                                               chip superio/winbond/w83627ehg
-                                                       device pnp 2e.0 on #  Floppy
-                                                               io 0x60 = 0x3f0
-                                                               irq 0x70 = 6
-                                                               drq 0x74 = 2
-                                                       end
-                                                       device pnp 2e.1 on #  Parallel Port
-                                                               io 0x60 = 0x378
-                                                               irq 0x70 = 7
-                                                               drq 0x74 = 3
-                                                       end
-                                                       device pnp 2e.2 on #  Com1
-                                                               io 0x60 = 0x3f8
-                                                               irq 0x70 = 4
-                                                       end
-                                                       device pnp 2e.3 off #  Com2
-                                                               io 0x60 = 0x2f8
-                                                               irq 0x70 = 3
-                                                       end
-                                                       device pnp 2e.5 off #keyb OFF
-                                                       end
-                                                       device pnp 2e.106 off #  SERIAL_FLASH
-                                                               io 0x60 = 0x100
-                                                       end
-
-                                                       device pnp 2e.007 off #GPIO1 off
-                                                       end
-                                                       device pnp 2e.107 on #GAME on
-                                                               io 0x60 = 0x201
-                                                       end
-                                                       device pnp 2e.207 on #MIDI on
-                                                               io 0x62 = 0x330
-                                                               irq 0x70 = 0xa
-                                                       end
-                                                       device pnp 2e.307 off #GPIO6 off
-                                                       end
-                                                       device pnp 2e.8 off end #  WDTO_PLED
-                                                       device pnp 2e.009 on #GPIO2 on Logical device 9 is in sio_setup
-                                                       end
-                                                       device pnp 2e.109 off #GPIO3 off
-                                                       end
-                                                       device pnp 2e.209 off #GPIO4 off
-                                                       end
-                                                       device pnp 2e.309 on #GPIO5 on
-                                                       end
-                                                       device pnp 2e.a off end #  ACPI
-                                                       device pnp 2e.b on #  HW Monitor
-                                                               io 0x60 = 0x290
-                                                               irq 0x70 = 0
-                                                       end
-                                               end #end SIO
-                                       end #end 11
-
-                                       device pci 12.0 off end # VIA LAN is disabled, Asus used other chip
-                               end
-
-                               chip southbridge/via/k8t890
-				end
-
-                       end #  device pci 18.0
-                       device pci 18.1 on end
-                       device pci 18.2 on end
-                       device pci 18.3 on end
-               end #mc0
-
-       end # pci_domain
-
-end # root_complex
+        chip southbridge/via/k8t890		# "Southbridge" K8T890
+        end
+      end
+      device pci 18.1 on end
+      device pci 18.2 on end
+      device pci 18.3 on end
+    end
+  end
+end
diff --git a/src/mainboard/asus/a8v-e_se/Options.lb b/src/mainboard/asus/a8v-e_se/Options.lb
index b6c5cea799..e9a623acf1 100644
--- a/src/mainboard/asus/a8v-e_se/Options.lb
+++ b/src/mainboard/asus/a8v-e_se/Options.lb
@@ -43,11 +43,9 @@ uses XIP_ROM_SIZE
 uses XIP_ROM_BASE
 uses STACK_SIZE
 uses HEAP_SIZE
-##uses USE_OPTION_TABLE
-##uses CONFIG_LB_MEM_TOPK
-
+# uses USE_OPTION_TABLE
+# uses CONFIG_LB_MEM_TOPK
 uses HAVE_ACPI_TABLES
-
 uses LB_CKS_RANGE_START
 uses LB_CKS_RANGE_END
 uses LB_CKS_LOC
@@ -75,242 +73,96 @@ uses CONFIG_GDB_STUB
 uses CONFIG_CHIP_NAME
 uses CONFIG_CONSOLE_VGA
 uses CONFIG_PCI_ROM_RUN
-#bx_b001- uses K8_HW_MEM_HOLE_SIZEK
+# bx_b001- uses K8_HW_MEM_HOLE_SIZEK
 uses K8_HT_FREQ_1G_SUPPORT
-
 uses USE_DCACHE_RAM
 uses DCACHE_RAM_BASE
 uses DCACHE_RAM_SIZE
 uses DCACHE_RAM_GLOBAL_VAR_SIZE
 uses CONFIG_USE_INIT
-
 uses ENABLE_APIC_EXT_ID
 uses APIC_ID_OFFSET
 uses LIFT_BSP_APIC_ID
-
 uses HT_CHAIN_UNITID_BASE
 uses HT_CHAIN_END_UNITID_BASE
-#bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
+# bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
-#bx_b005+
+# bx_b005+
 uses SB_HT_CHAIN_ON_BUS0
-
 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-#512K bytes
-default ROM_SIZE=512 * 1024
-
-#1M bytes
-#bx- default ROM_SIZE=1024 * 1024
-
-##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-#256K
-default FALLBACK_SIZE=256 * 1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default HAVE_HARD_RESET=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default HAVE_PIRQ_TABLE=0
-default IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default HAVE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default HAVE_OPTION_TABLE=0
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-default CONFIG_MAX_PHYSICAL_CPUS=1
-default CONFIG_LOGICAL_CPUS=1
-
-#acpi
-default HAVE_ACPI_TABLES=1
-
-#CHIP_NAME ?
-#default CONFIG_CHIP_NAME=1
-
-#1G memory hole
-#bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000
-
-#Opteron K8 1G HT Support
-default K8_HT_FREQ_1G_SUPPORT=1
-
-##HT Unit ID offset, default is 1, the typical one
-default HT_CHAIN_UNITID_BASE=0x0
-
-##real SB Unit ID, default is 0x20, mean dont touch it at last
-#default HT_CHAIN_END_UNITID_BASE=0x0
-
-#make the SB HT chain on bus 0, default is not (0)
-#bx_b001- default K8_SB_HT_CHAIN_ON_BUS0=2
-
-##bx_b005+ make the SB HT chain on bus 0
-default SB_HT_CHAIN_ON_BUS0=1
-
-##only offset for SB chain?, default is yes(1)
-default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#VGA
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xcc000
-default DCACHE_RAM_SIZE=0x4000
-default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-default ENABLE_APIC_EXT_ID=0
-default APIC_ID_OFFSET=0x10
-default LIFT_BSP_APIC_ID=0
-
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default MAINBOARD_PART_NUMBER="A8V-E SE"
-default MAINBOARD_VENDOR="ASUS"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1043
-#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
-
-###
-### coreboot layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default ROM_SIZE = 512 * 1024
+default FALLBACK_SIZE = 256 * 1024
+default HAVE_FALLBACK_BOOT = 1
+default HAVE_HARD_RESET = 0
+default HAVE_PIRQ_TABLE = 0
+default IRQ_SLOT_COUNT = 11	# FIXME?
+default HAVE_MP_TABLE = 1
+default HAVE_OPTION_TABLE = 0	# FIXME
+# Move the default coreboot CMOS range off of AMD RTC registers.
+default LB_CKS_RANGE_START = 49
+default LB_CKS_RANGE_END = 122
+default LB_CKS_LOC = 123
+default CONFIG_SMP = 1
+default CONFIG_MAX_CPUS = 2
+default CONFIG_MAX_PHYSICAL_CPUS = 1
+default CONFIG_LOGICAL_CPUS = 1
+default HAVE_ACPI_TABLES = 1
+# default CONFIG_CHIP_NAME = 1
+
+# 1G memory hole
+# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
+
+# Opteron K8 1G HT support
+default K8_HT_FREQ_1G_SUPPORT = 1
+
+# HT Unit ID offset, default is 1, the typical one.
+default HT_CHAIN_UNITID_BASE = 0x0
+
+# Real SB Unit ID, default is 0x20, mean don't touch it at last.
+# default HT_CHAIN_END_UNITID_BASE = 0x0
+
+# Make the SB HT chain on bus 0, default is not (0).
+# bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2
+
+# bx_b005+ make the SB HT chain on bus 0.
+default SB_HT_CHAIN_ON_BUS0 = 1
+
+# Only offset for SB chain?, default is yes(1).
+default SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
+
+default CONFIG_CONSOLE_VGA = 1		# Needed for VGA.
+default CONFIG_PCI_ROM_RUN = 1		# Needed for VGA.
+default USE_DCACHE_RAM = 1
+default DCACHE_RAM_BASE = 0xcc000
+default DCACHE_RAM_SIZE = 0x4000
+default DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
+default CONFIG_USE_INIT = 0
+default ENABLE_APIC_EXT_ID = 0
+default APIC_ID_OFFSET = 0x10
+default LIFT_BSP_APIC_ID = 0
+default CONFIG_IOAPIC = 1
+default MAINBOARD_VENDOR = "ASUS"
+default MAINBOARD_PART_NUMBER = "A8V-E SE"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
+# default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234	# FIXME
 default ROM_IMAGE_SIZE = 64 * 1024
-
-##
-## Use a small 8K stack
-##
-default STACK_SIZE= 8 * 1024
-
-##
-## Use a small 256K heap
-##
-default HEAP_SIZE=256 * 1024
-
-#more 1M for pgtbl
-##default CONFIG_LB_MEM_TOPK=2048
-
-##
-## Only use the option table in a normal image
-##
-##default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default _RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
+default STACK_SIZE = 8 * 1024
+default HEAP_SIZE = 256 * 1024
+# More 1M for pgtbl.
+# default CONFIG_LB_MEM_TOPK = 2048
+default _RAMBASE = 0x00004000
+# default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
 default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
-
-# Select the serial console base port
-default TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
+default CC = "$(CROSS_COMPILE)gcc -m32"
+default HOSTCC = "gcc"
+default CONFIG_GDB_STUB = 0
+default CONFIG_CONSOLE_SERIAL8250 = 1
+default TTYS0_BAUD = 115200
+default TTYS0_BASE = 0x3f8
+default TTYS0_LCS = 0x3		# 8n1
+default DEFAULT_CONSOLE_LOGLEVEL = 8
+default MAXIMUM_CONSOLE_LOGLEVEL = 8
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
 end
diff --git a/src/mainboard/asus/a8v-e_se/acpi_tables.c b/src/mainboard/asus/a8v-e_se/acpi_tables.c
index fa76d401f6..86fee0c99a 100644
--- a/src/mainboard/asus/a8v-e_se/acpi_tables.c
+++ b/src/mainboard/asus/a8v-e_se/acpi_tables.c
@@ -1,6 +1,7 @@
 /*
  * This file is part of the coreboot project.
- * written by Stefan Reinauer <stepan@openbios.org>
+ *
+ * Written by Stefan Reinauer <stepan@openbios.org>.
  * ACPI FADT, FACS, and DSDT table support added by 
  *
  * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
@@ -27,7 +28,6 @@
 #include <arch/smp/mpspec.h>
 #include <device/device.h>
 #include <device/pci_ids.h>
-
 #include <../../../southbridge/via/vt8237r/vt8237r.h>
 #include <../../../southbridge/via/k8t890/k8t890.h>
 
@@ -37,6 +37,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 {
 	device_t dev;
 	struct resource *res;
+
 	dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5, 0);
 	if (!dev)
 		return current;
@@ -53,36 +54,32 @@ unsigned long acpi_fill_madt(unsigned long current)
 {
 	unsigned int gsi_base = 0x18;
 
-	/* create all subtables for processors */
+	/* Create all subtables for processors. */
 	current = acpi_create_madt_lapics(current);
 
-	/* Write SB IOAPIC */
-	current +=
-	    acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, VT8237R_APIC_ID,
-				    VT8237R_APIC_BASE, 0);
+	/* Write SB IOAPIC. */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				VT8237R_APIC_ID, VT8237R_APIC_BASE, 0);
 
-	/* Write NB IOAPIC */
-	current +=
-	    acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, K8T890_APIC_ID,
-				    K8T890_APIC_BASE, gsi_base);
-	/* IRQ9 ACPI active low */
+	/* Write NB IOAPIC. */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
+
+	/* IRQ9 ACPI active low. */
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
+		current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
 
-	/* IRQ0 -> APIC IRQ2 */
+	/* IRQ0 -> APIC IRQ2. */
 	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
 						current, 0, 0, 2, 0x0);	
 
-	/* create all subtables for processors */
-	current =
-	    acpi_create_madt_lapic_nmis(current,
-					MP_IRQ_TRIGGER_EDGE |
-					MP_IRQ_POLARITY_HIGH, 1);
+	/* Create all subtables for processors. */
+	current = acpi_create_madt_lapic_nmis(current,
+			MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
 
 	return current;
 }
 
-
 unsigned long write_acpi_tables(unsigned long start)
 {
 	unsigned long current;
@@ -96,27 +93,25 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_facs_t *facs;
 	acpi_header_t *dsdt;
 
-	/* Align ACPI tables to 16byte */
+	/* Align ACPI tables to 16 byte. */
 	start = (start + 0x0f) & -0x10;
 	current = start;
 
 	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
 
-	/* We need at least an RSDP and an RSDT Table */
+	/* We need at least an RSDP and an RSDT table. */
 	rsdp = (acpi_rsdp_t *) current;
 	current += sizeof(acpi_rsdp_t);
 	rsdt = (acpi_rsdt_t *) current;
 	current += sizeof(acpi_rsdt_t);
 
-	/* clear all table memory */
+	/* Clear all table memory. */
 	memset((void *) start, 0, current - start);
 
 	acpi_write_rsdp(rsdp, rsdt);
 	acpi_write_rsdt(rsdt);
 
-	/*
-	 * We explicitly add these tables later on:
-	 */
+	/* We explicitly add these tables later on: */
 	printk_debug("ACPI:     * FACS\n");
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
@@ -126,7 +121,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	current += ((acpi_header_t *) AmlCode)->length;
 	memcpy((void *) dsdt, (void *) AmlCode,
 	       ((acpi_header_t *) AmlCode)->length);
-	dsdt->checksum = 0;	// don't trust intel iasl compiler to get this right
+	dsdt->checksum = 0;	/* Don't trust iasl to get this right. */
 	dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
 	printk_debug("ACPI:     * DSDT @ %08x Length %x\n", dsdt,
 		     dsdt->length);
@@ -144,7 +139,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_create_hpet(hpet);
 	acpi_add_table(rsdt, hpet);
 
-	/* If we want to use HPET Timers Linux wants an MADT */
+	/* If we want to use HPET timers Linux wants an MADT. */
 	printk_debug("ACPI:    * MADT\n");
 	madt = (acpi_madt_t *) current;
 	acpi_create_madt(madt);
@@ -157,7 +152,6 @@ unsigned long write_acpi_tables(unsigned long start)
 	current += mcfg->header.length;
 	acpi_add_table(rsdt, mcfg);
 
-	/* SRAT */
 	printk_debug("ACPI:    * SRAT\n");
 	srat = (acpi_srat_t *) current;
 	acpi_create_srat(srat);
diff --git a/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c b/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
index ca0fbd9197..796b87f581 100644
--- a/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
+++ b/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
@@ -2,10 +2,9 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2006 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
+ * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
  * Copyright (C) 2006 MSI
- * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
- *
+ * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz> 
  *
  * This program is free software; you can redistribute it and/or modify
@@ -32,15 +31,16 @@
 
 unsigned int get_sbdn(unsigned bus);
 
-//used by raminit
+/* Used by raminit. */
 #define QRANK_DIMM_SUPPORT 1
 
-//used by init_cpus and fidvid
+/* Used by init_cpus and fidvid */
 #define K8_SET_FIDVID 1
-//if we want to wait for core1 done before DQS training, set it to 0
+
+/* If we want to wait for core1 done before DQS training, set it to 0. */
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-//#define DEBUG_SMBUS 1
+/* #define DEBUG_SMBUS 1 */
 
 #include <stdint.h>
 #include <device/pci_def.h>
@@ -50,31 +50,23 @@ unsigned int get_sbdn(unsigned bus);
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
-
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #if CONFIG_USE_INIT == 0
 #include "lib/memcpy.c"
 #endif
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "northbridge/amd/amdk8/early_ht.c"
-
-
 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
-
 #include "cpu/amd/mtrr/amd_earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
@@ -90,7 +82,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
 
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
 	return smbus_read_byte(device, address);
@@ -103,34 +94,27 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "sdram/generic_sdram.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "southbridge/via/k8t890/k8t890_early_car.c"
-
 #include "cpu/amd/car/copy_and_run.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
-
 #include "northbridge/amd/amdk8/resourcemap.c"
 
-
 void activate_spd_rom(const struct mem_controller *ctrl)
 {
-
 }
 
 void hard_reset(void)
 {
-	print_info("NO HARD RESET  FIX ME!\n");
+	print_info("NO HARD RESET. FIX ME!\n");
 }
 
 void soft_reset(void)
 {
 	uint8_t tmp;
+
 	set_bios_reset();
 	print_debug("soft reset \r\n");
 
@@ -154,26 +138,29 @@ unsigned int get_sbdn(unsigned bus)
 	return (dev >> 15) & 0x1f;
 }
 
-
-void sio_init(void) {
+void sio_init(void)
+{
 	u8 reg;
 
 	pnp_enter_ext_func_mode(SERIAL_DEV);
+	/* We have 24MHz input. */
 	reg = pnp_read_config(SERIAL_DEV, 0x24);
-	pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));	/* we have 24MHz input */
-
-	reg = pnp_read_config(SERIAL_DEV, 0x2A);
-	pnp_write_config(SERIAL_DEV, 0x2A, (reg | 1));	/* we have GPIO for KB/MS PIN */
-
-	reg = pnp_read_config(SERIAL_DEV, 0x2C);
-	pnp_write_config(SERIAL_DEV, 0x2C, (reg | 0xf0));	/* we have all RESTOUT and even some reserved bits too */
-
+	pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
+	/* We have GPIO for KB/MS pin. */
+	reg = pnp_read_config(SERIAL_DEV, 0x2a);
+	pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
+	/* We have all RESTOUT and even some reserved bits, too. */
+	reg = pnp_read_config(SERIAL_DEV, 0x2c);
+	pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
 	pnp_exit_ext_func_mode(SERIAL_DEV);
 
 	pnp_enter_ext_func_mode(ACPI_DEV);
 	pnp_set_logical_device(ACPI_DEV);
+	/*
+	 * Set the delay rising time from PWROK_LP to PWROK_ST to
+	 * 300 - 600ms, and 0 to vice versa.
+	 */
 	reg = pnp_read_config(ACPI_DEV, 0xe6);
-	/* Set the delay rising time from PWROK_LP to PWROK_ST to 300 - 600ms, and 0 to vice versa */ 
 	pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
 	/* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
 	reg = pnp_read_config(ACPI_DEV, 0xe4);
@@ -182,15 +169,14 @@ void sio_init(void) {
 
 	pnp_enter_ext_func_mode(GPIO_DEV);
 	pnp_set_logical_device(GPIO_DEV);
-	
-	/* set memory voltage to 2.75V, vcore offset + 100mV, 1.5V Chipset voltage */
-	pnp_write_config(GPIO_DEV, 0x30, 0x9);	/* Enable GPIO 2 & GPIO 5 */
-	pnp_write_config(GPIO_DEV, 0xe2, 0x0);	/* no inversion */
-	pnp_write_config(GPIO_DEV, 0xe5, 0x0);	/* no inversion */
-	pnp_write_config(GPIO_DEV, 0xe3, 0x3);	/* 0000 0011 0=output 1=input */
-	pnp_write_config(GPIO_DEV, 0xe0, 0xde);	/* 1101110  0=output 1=input */
-	pnp_write_config(GPIO_DEV, 0xe1, 0x1);	/* set output val */
-	pnp_write_config(GPIO_DEV, 0xe4, 0xb4);	/* set output val  1011 0100 */
+	/* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
+	pnp_write_config(GPIO_DEV, 0x30, 0x09);	/* Enable GPIO 2 & GPIO 5. */
+	pnp_write_config(GPIO_DEV, 0xe2, 0x00);	/* No inversion */
+	pnp_write_config(GPIO_DEV, 0xe5, 0x00);	/* No inversion */
+	pnp_write_config(GPIO_DEV, 0xe3, 0x03);	/* 0000 0011, 0=output 1=input */
+	pnp_write_config(GPIO_DEV, 0xe0, 0xde);	/* 1101 1110, 0=output 1=input */
+	pnp_write_config(GPIO_DEV, 0xe1, 0x01);	/* Set output val. */
+	pnp_write_config(GPIO_DEV, 0xe4, 0xb4);	/* Set output val (1011 0100). */
 	pnp_exit_ext_func_mode(GPIO_DEV);
 }
 
@@ -198,8 +184,8 @@ void sio_init(void) {
 
 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-//        unsigned last_boot_normal_x = last_boot_normal();
-//FIXME
+	/* unsigned last_boot_normal_x = last_boot_normal(); */
+	/* FIXME */
 	unsigned last_boot_normal_x = 1;
 
 	sio_init();
@@ -209,56 +195,50 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	print_info("now booting... fallback\r\n");
 
-	/* Is this a cpu only reset? or Is this a secondary cpu? */
+	/* Is this a CPU only reset? Or is this a secondary CPU? */
 	if ((cpu_init_detectedx) || (!boot_cpu())) {
-		if (last_boot_normal_x) {
+		if (last_boot_normal_x)
 			goto normal_image;
-		} else {
+		else
 			goto fallback_image;
-		}
 	}
 
-	/* Nothing special needs to be done to find bus 0 */
-	/* Allow the HT devices to be found */
-
+	/* Nothing special needs to be done to find bus 0. */
+	/* Allow the HT devices to be found. */
 	enumerate_ht_chain();
 
-	/* Is this a deliberate reset by the bios */
+	/* Is this a deliberate reset by the BIOS? */
 	if (bios_reset_detected() && last_boot_normal_x) {
 		goto normal_image;
 	}
-	/* This is the primary cpu how should I boot? */
+	/* This is the primary CPU, how should I boot? */
 	else if (do_normal_boot()) {
 		goto normal_image;
 	} else {
 		goto fallback_image;
 	}
-      normal_image:
-	//print_info("JMP normal image\r\n");
 
-	__asm__ volatile ("jmp __normal_image":	/* outputs */
-			  :"a" (bist), "b"(cpu_init_detectedx)	/* inputs */
-	    );
+normal_image:
+	/* print_info("JMP normal image\r\n"); */
+
+	__asm__ __volatile__("jmp __normal_image":
+			     :"a" (bist), "b" (cpu_init_detectedx));
 
-      fallback_image:
+fallback_image:
 	;
 }
 #endif
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
-void cache_as_ram_main(unsigned long bist,
-		       unsigned long cpu_init_detectedx)
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-
 #if USE_FALLBACK_IMAGE == 1
 	failover_process(bist, cpu_init_detectedx);
 #endif
 	real_main(bist, cpu_init_detectedx);
-
 }
 
-
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	static const uint16_t spd_addr[] = {
@@ -272,8 +252,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	unsigned bsp_apicid = 0;
 	int needs_reset = 0;
 	struct sys_info *sysinfo =
-	    (DCACHE_RAM_BASE + DCACHE_RAM_SIZE -
-	     DCACHE_RAM_GLOBAL_VAR_SIZE);
+	    (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
 	char *p;
 
 	sio_init();
@@ -283,23 +262,25 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	print_info("now booting... real_main\r\n");
 
-	if (bist == 0) {
+	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-	}
-	/* Halt if there was a built in self test failure */
+
+	/* Halt if there was a built in self test failure. */
 	report_bist_failure(bist);
+
 	setup_default_resource_map();
 	setup_coherent_ht_domain();
 	wait_all_core0_started();
+
 	print_info("now booting... Core0 started\r\n");
 
 #if CONFIG_LOGICAL_CPUS==1
-	// It is said that we should start core1 after all core0 launched
+	/* It is said that we should start core1 after all core0 launched. */
 	start_other_cores();
 	wait_all_other_cores_started(bsp_apicid);
 #endif
 	init_timer();
-	ht_setup_chains_x(sysinfo);	// it will init sblnk and sbbusn, nodes, sbdn
+	ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
 
 	enable_fid_change();
 	init_fidvid_bsp(bsp_apicid);
@@ -307,20 +288,22 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	needs_reset = optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
 
-	/* Fixme it assumes that 1000MHz LDT is selected. */
+	/* FIXME: Assumes that 1000MHz LDT is selected. */
 	needs_reset |= k8t890_early_setup_car(16, 0x6);
 
 	if (needs_reset) {
 		print_debug("ht reset -\r\n");
 		soft_reset();
 	}
-	/* stop the APs so we can start them later in init */
-        allow_all_aps_stop(bsp_apicid);
-	/* It's the time to set ctrl now; */
+
+	/* Stop the APs so we can start them later in init. */
+	allow_all_aps_stop(bsp_apicid);
+
+	/* It's the time to set ctrl now. */
 	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
 	enable_smbus();
 	memreset_setup();
 	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 	post_cache_as_ram();
 }
-
diff --git a/src/mainboard/asus/a8v-e_se/chip.h b/src/mainboard/asus/a8v-e_se/chip.h
index 77f099cd95..101113437d 100644
--- a/src/mainboard/asus/a8v-e_se/chip.h
+++ b/src/mainboard/asus/a8v-e_se/chip.h
@@ -20,5 +20,4 @@
 extern struct chip_operations mainboard_asus_a8v_e_se_ops;
 
 struct mainboard_asus_a8v_e_se_config {
-     
 };
diff --git a/src/mainboard/asus/a8v-e_se/dsdt.asl b/src/mainboard/asus/a8v-e_se/dsdt.asl
index 220e6c81e4..144fcf2459 100644
--- a/src/mainboard/asus/a8v-e_se/dsdt.asl
+++ b/src/mainboard/asus/a8v-e_se/dsdt.asl
@@ -1,12 +1,11 @@
 /*
  * This file is part of the coreboot project.
  *
- * Minimalist ACPI DSDT table for EPIA-M / MII
  * (C) Copyright 2004 Nick Barker <Nick.Barker9@btinternet.com>
- *
  * (C) Copyright 2007 Rudolf Marek <r.marek@assembler.cz>
  *
- * ISA portions taken from QEMU acpi-dsdt.dsl  
+ * ISA portions taken from QEMU acpi-dsdt.dsl.
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License v2 as published by
  * the Free Software Foundation.
@@ -21,16 +20,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-
 DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
 {
-
-
-
-
-	/*  
-	 * Define the main processor
-	 */
+	/* Define the main processor.*/
 	Scope (\_PR)
 	{
 		Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}
@@ -40,206 +32,178 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
 	/* For now only define 2 power states:
 	 *  - S0 which is fully on
 	 *  - S5 which is soft off
-	 * any others would involve declaring the wake up methods
+	 * Any others would involve declaring the wake up methods.
 	 */
-	Name (\_S0, Package () {0x00, 0x00, 0x00, 0x00 })
-	Name (\_S5, Package () {0x02, 0x02, 0x00, 0x00 })
+	Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+	Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
 
 	/* Root of the bus hierarchy */
 	Scope (\_SB)
-    	{
-		/* top PCI device */
+	{
+		/* Top PCI device */
 		Device (PCI0)
 		{
 			Name (_HID, EisaId ("PNP0A03"))
 			Name (_ADR, 0x00)
 			Name (_UID, 0x00)
 			Name (_BBN, 0x00)
-			
-			/* PCI Routing Table */
-			//aaa
-			Name (_PRT, Package () {
-	                    Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, //slot 0xB
-        	            Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
-                	    Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
-	                    Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },
-        	            Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, //Slot 0xC
-                	    Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },
-                	    Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },
-			    Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },
-        	            Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, //Slot 0xD
-                	    Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
-                	    Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
-			    Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
-        	            Package (0x04) { 0x000F0000, 0x01, 0x00, 0x14 }, //0xf SATA IRQ 20
-                	    Package (0x04) { 0x000F0001, 0x00, 0x00, 0x14 }, //0xf NAtive IDE IRQ 20
-        	            Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, //USB routing
-                	    Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
-                	    Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
-			    Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
-			    Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, //AC97 MC97
-        	            Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, //PCIE16 bridge IRQ27
-                	    Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
-                	    Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
-			    Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
-        	            Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, //PCIE bridge IRQ31
-                	    Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, //IRQ36
-                	    Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, //IRQ39
-			    Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } //IRQ43
-            		})
 
-		
-		Device (PEGG)
-		{
-			Name (_ADR, 0x00020000)
-			Name (_UID, 0x00)
-			Name (_BBN, 0x02)
-			
-			Name (_PRT, Package () {
-	                    Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, //PCIE IRQ24-IRQ27
-        	            Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
-                	    Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
-	                    Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
-			})	
-		} //end of PCIEG
-
-		Device (PEX0)
-		{
-			Name (_ADR, 0x00030000)
-			Name (_UID, 0x00)
-			Name (_BBN, 0x03)
-			
-			Name (_PRT, Package () {
-	                    Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, //PCIE IRQ28-IRQ31
-        	            Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
-                	    Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
-	                    Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
-			})	
-		} //end of PEX0
-
-		Device (PEX1)
-		{
-			Name (_ADR, 0x00030001)
-			Name (_UID, 0x00)
-			Name (_BBN, 0x04)
-			
-			Name (_PRT, Package () {
-	                    Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, //PCIE IRQ32-IRQ35
-        	            Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
-                	    Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
-	                    Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
-			})	
-		} //end f PEX1
-
-		Device (PEX2)
-		{
-			Name (_ADR, 0x00030002)
-			Name (_UID, 0x00)
-			Name (_BBN, 0x05)
-			
-			Name (_PRT, Package () {
-	                    Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, //PCIE IRQ36-IRQ39
-        	            Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
-                	    Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
-	                    Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
-			})	
-		} //end f PEX2
-
-		Device (PEX3)
-		{
-			Name (_ADR, 0x00030003)
-			Name (_UID, 0x00)
-			Name (_BBN, 0x06)
-			
+			/* PCI Routing Table */
+			/* aaa */
 			Name (_PRT, Package () {
-	                    Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, //PCIE IRQ40-IRQ43
-        	            Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },
-                	    Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },
-	                    Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },
-			})	
-		} //end f PEX3
-
-        Device (ISA) {
-            Name (_ADR, 0x00110000)
-        
-            /* Keyboard seems to be important for WinXP install */
-            Device (KBD)
-            {
-                Name (_HID, EisaId ("PNP0303"))
-                Method (_STA, 0, NotSerialized)
-                {
-                    Return (0x0f)
-                }
-
-                Method (_CRS, 0, NotSerialized)
-                {
-                     Name (TMP, ResourceTemplate ()
-                     {
-                    IO (Decode16,
-                        0x0060,             // Address Range Minimum
-                        0x0060,             // Address Range Maximum
-                        0x01,               // Address Alignment
-                        0x01,               // Address Length
-                        )
-                    IO (Decode16,
-                        0x0064,             // Address Range Minimum
-                        0x0064,             // Address Range Maximum
-                        0x01,               // Address Alignment
-                        0x01,               // Address Length
-                        )
-                    IRQNoFlags ()
-                        {1}
-                    })
-                    Return (TMP)
-                }
-            }
-
-	    /* PS/2 mouse */
-            Device (MOU) 
-            {
-                Name (_HID, EisaId ("PNP0F13"))
-                Method (_STA, 0, NotSerialized)
-                {
-                    Return (0x0f)
-                }
-
-                Method (_CRS, 0, NotSerialized)
-                {
-                    Name (TMP, ResourceTemplate ()
-                    {
-                         IRQNoFlags () {12}
-                    })
-                    Return (TMP)
-                }
-            }
-
-	    /* PS/2 floppy controller */
-	    Device (FDC0)
-	    {
-	        Name (_HID, EisaId ("PNP0700"))
-		Method (_STA, 0, NotSerialized)
-		{
-		    Return (0x0F)
-		}
-		Method (_CRS, 0, NotSerialized)
-		{
-		    Name (BUF0, ResourceTemplate ()
-                    {
-                        IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
-                        IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
-                        IRQNoFlags () {6}
-                        DMA (Compatibility, NotBusMaster, Transfer8) {2}
-                    })
-		    Return (BUF0)
+				Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */
+				Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
+				Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
+				Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },
+				Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */
+				Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },
+				Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },
+				Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },
+				Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */
+				Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
+				Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
+				Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
+				Package (0x04) { 0x000F0000, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */
+				Package (0x04) { 0x000F0001, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
+				Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
+				Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
+				Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
+				Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
+				Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */
+				Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
+				Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
+				Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
+				Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
+				Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
+				Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
+				Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
+				Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B }  /* IRQ43 */
+			})
+
+			Device (PEGG)
+			{
+				Name (_ADR, 0x00020000)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x02)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
+				})
+			}
+
+			Device (PEX0)
+			{
+				Name (_ADR, 0x00030000)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x03)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
+				})
+			}
+
+			Device (PEX1)
+			{
+				Name (_ADR, 0x00030001)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x04)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
+				})
+			}
+
+			Device (PEX2)
+			{
+				Name (_ADR, 0x00030002)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x05)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
+				})
+			}
+
+			Device (PEX3)
+			{
+				Name (_ADR, 0x00030003)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x06)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },
+				})
+			}
+
+			Device (ISA) {
+				Name (_ADR, 0x00110000)
+
+				/* PS/2 keyboard (seems to be important for WinXP install) */
+				Device (KBD)
+				{
+					Name (_HID, EisaId ("PNP0303"))
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0f)
+					}
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (TMP, ResourceTemplate () {
+							IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+							IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+							IRQNoFlags () {1}
+						})
+						Return (TMP)
+					}
+				}
+
+				/* PS/2 mouse */
+				Device (MOU)
+				{
+					Name (_HID, EisaId ("PNP0F13"))
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0f)
+					}
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (TMP, ResourceTemplate () {
+						     IRQNoFlags () {12}
+						})
+						Return (TMP)
+					}
+				}
+
+				/* PS/2 floppy controller */
+				Device (FDC0)
+				{
+					Name (_HID, EisaId ("PNP0700"))
+					Method (_STA, 0, NotSerialized)
+					{
+						Return (0x0f)
+					}
+					Method (_CRS, 0, NotSerialized)
+					{
+						Name (BUF0, ResourceTemplate () {
+							IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
+							IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
+							IRQNoFlags () {6}
+							DMA (Compatibility, NotBusMaster, Transfer8) {2}
+						})
+						Return (BUF0)
+					}
+				}
+			}
 		}
-	    } //FD END
-
-        } //ISA END
-
-	} // End of PCI0
-		
-		
-	} // End of _SB
-
-} // End of Definition Block
-
+	}
+}
diff --git a/src/mainboard/asus/a8v-e_se/fadt.c b/src/mainboard/asus/a8v-e_se/fadt.c
index d4e3003512..a5386d7880 100644
--- a/src/mainboard/asus/a8v-e_se/fadt.c
+++ b/src/mainboard/asus/a8v-e_se/fadt.c
@@ -1,7 +1,8 @@
 /*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- * (C) Copyright 2004 Nick Barker <nick.barker9@btinternet.com>
- * (C) Copyright 2007 Rudolf Marek <r.marek@assembler.cz>
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker <nick.barker9@btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -15,15 +16,17 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
 #include <string.h>
 #include <arch/acpi.h>
 #include <../../../southbridge/via/vt8237r/vt8237r.h>
 
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+/**
+ * Create the Fixed ACPI Description Tables (FADT) for this board.
+ */
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
 {
 	acpi_header_t *header = &(fadt->header);
 
@@ -146,6 +149,5 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
 	fadt->x_gpe1_blk.addrl = 0x0;
 	fadt->x_gpe1_blk.addrh = 0x0;
 
-	header->checksum =
-	    acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
+	header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
 }
diff --git a/src/mainboard/asus/a8v-e_se/mainboard.c b/src/mainboard/asus/a8v-e_se/mainboard.c
index 79ea4f0e3b..c06fbffd60 100644
--- a/src/mainboard/asus/a8v-e_se/mainboard.c
+++ b/src/mainboard/asus/a8v-e_se/mainboard.c
@@ -21,7 +21,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <device/pci_ops.h>
 #include "chip.h"
 
 #if CONFIG_CHIP_NAME == 1
diff --git a/src/mainboard/asus/a8v-e_se/mptable.c b/src/mainboard/asus/a8v-e_se/mptable.c
index 1cb7739cf9..bdf1d7cc50 100644
--- a/src/mainboard/asus/a8v-e_se/mptable.c
+++ b/src/mainboard/asus/a8v-e_se/mptable.c
@@ -17,43 +17,42 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#include <arch/smp/mpspec.h>
 #include <string.h>
 #include <stdint.h>
-
+#include <arch/smp/mpspec.h>
 #include <../../../southbridge/via/vt8237r/vt8237r.h>
 #include <../../../southbridge/via/k8t890/k8t890.h>
 
 void *smp_write_config_table(void *v)
 {
-        static const char sig[4] = "PCMP";
-        static const char oem[8] = "LNXB    ";
-        static const char productid[12] = "A8V-E SE    ";
-        struct mp_config_table *mc;
+	static const char sig[4] = "PCMP";
+	static const char oem[8] = "LNXB    ";
+	static const char productid[12] = "A8V-E SE    ";
+	struct mp_config_table *mc;
 	unsigned int conforms = 0;
 	int bus_isa = 42;
 
-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-        memset(mc, 0, sizeof(*mc));
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	memset(mc, 0, sizeof(*mc));
 
-        memcpy(mc->mpc_signature, sig, sizeof(sig));
-        mc->mpc_length = sizeof(*mc); /* initially just the header */
-        mc->mpc_spec = 0x04;
-        mc->mpc_checksum = 0; /* not yet computed */
-        memcpy(mc->mpc_oem, oem, sizeof(oem));
-        memcpy(mc->mpc_productid, productid, sizeof(productid));
-        mc->mpc_oemptr = 0;
-        mc->mpc_oemsize = 0;
-        mc->mpc_entry_count = 0; /* No entries yet... */
-        mc->mpc_lapic = LAPIC_ADDR;
-        mc->mpe_length = 0;
-        mc->mpe_checksum = 0;
-        mc->reserved = 0;
+	memcpy(mc->mpc_signature, sig, sizeof(sig));
+	mc->mpc_length = sizeof(*mc); /* Initially just the header. */
+	mc->mpc_spec = 0x04;
+	mc->mpc_checksum = 0; /* Not yet computed. */
+	memcpy(mc->mpc_oem, oem, sizeof(oem));
+	memcpy(mc->mpc_productid, productid, sizeof(productid));
+	mc->mpc_oemptr = 0;
+	mc->mpc_oemsize = 0;
+	mc->mpc_entry_count = 0; /* No entries yet. */
+	mc->mpc_lapic = LAPIC_ADDR;
+	mc->mpe_length = 0;
+	mc->mpe_checksum = 0;
+	mc->reserved = 0;
 
-        smp_write_processors(mc);
+	smp_write_processors(mc);
 
 
-/*Bus:		Bus ID	Type*/
+	/* Bus:		Bus ID	Type */
 	smp_write_bus(mc, 0, "PCI   ");
 	smp_write_bus(mc, 1, "PCI   ");
 	smp_write_bus(mc, 2, "PCI   ");
@@ -62,12 +61,11 @@ void *smp_write_config_table(void *v)
 	smp_write_bus(mc, 5, "PCI   ");
 	smp_write_bus(mc, 6, "PCI   ");
 	smp_write_bus(mc, bus_isa, "ISA   ");
-/*I/O APICs:	APIC ID	Version	State		Address*/
 
+	/* I/O APICs:	APIC ID	Version	State		Address */
 	smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VT8237R_APIC_BASE);
 	smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, K8T890_APIC_BASE);
 
-
 	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, VT8237R_APIC_ID, 0x0);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, VT8237R_APIC_ID, 0x1);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, VT8237R_APIC_ID, 0x2);
@@ -142,14 +140,16 @@ void *smp_write_config_table(void *v)
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 2, K8T890_APIC_ID, 0x12);
 	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6,  (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);
 
-/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+	/* Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN# */
+	smp_write_intsrc(mc, mp_ExtINT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_intsrc(mc, mp_NMI,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
 	/* There is no extension information... */
 
-	/* Compute the checksums */
-	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+	/* Compute the checksums. */
+	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc),
+						mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+
 	return smp_next_mpe_entry(mc);
 }