coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

26 files changed, 52 insertions, 52 deletions

diff --git a/src/mainboard/asus/am1i-a/BiosCallOuts.c b/src/mainboard/asus/am1i-a/BiosCallOuts.c
index c8cc68a6cb..c01ea74997 100644
--- a/src/mainboard/asus/am1i-a/BiosCallOuts.c
+++ b/src/mainboard/asus/am1i-a/BiosCallOuts.c
@@ -99,7 +99,7 @@ static const CODEC_TBL_LIST CodecTableList[] =
 
 void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
 {
-	FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+	FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
 	FchParams_reset->Mode = 6;
 
 	/* Read SATA speed setting from CMOS */
diff --git a/src/mainboard/asus/am1i-a/OemCustomize.c b/src/mainboard/asus/am1i-a/OemCustomize.c
index f1bf60ea03..e001d43d4a 100644
--- a/src/mainboard/asus/am1i-a/OemCustomize.c
+++ b/src/mainboard/asus/am1i-a/OemCustomize.c
@@ -104,8 +104,8 @@ void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 {
 	FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
 
-	FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
-	FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+	FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
+	FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE);
 
 	FchReset->SataEnable = 1;
 	FchReset->IdeEnable = 0;
diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c
index 45e174c922..9e60ca758a 100644
--- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c
+++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c
@@ -39,7 +39,7 @@ const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
  * Copied from `/sys/class/sound/hwC1D0/init_pin_configs` when running
  * the vendor BIOS.
  */
-#if !IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_LE)
+#if !CONFIG(BOARD_ASUS_F2A85_M_LE)
 const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = {
 	{0x11, 0x99430140},
 	{0x12, 0x411111f0},
@@ -85,7 +85,7 @@ static const CODEC_TBL_LIST CodecTableList[] =
 
 void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset)
 {
-	FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
+	FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
 }
 
 void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env)
diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c
index 9d96753298..ec79fc832b 100644
--- a/src/mainboard/asus/f2a85-m/OemCustomize.c
+++ b/src/mainboard/asus/f2a85-m/OemCustomize.c
@@ -134,8 +134,8 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
 void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 {
 	FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
-	FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
-	FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
+	FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
+	FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE);
 }
 
 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
@@ -179,9 +179,9 @@ static CONST PSO_ENTRY ROMDATA MemoryTable_M_LE[] = {
 
 void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
 {
-	if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M) || IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO))
+	if (CONFIG(BOARD_ASUS_F2A85_M) || CONFIG(BOARD_ASUS_F2A85_M_PRO))
 		InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_M;
-	else if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_LE))
+	else if (CONFIG(BOARD_ASUS_F2A85_M_LE))
 		InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *) MemoryTable_M_LE;
 }
 
diff --git a/src/mainboard/asus/f2a85-m/acpi/routing.asl b/src/mainboard/asus/f2a85-m/acpi/routing.asl
index af8532fdc7..c0aef87a15 100644
--- a/src/mainboard/asus/f2a85-m/acpi/routing.asl
+++ b/src/mainboard/asus/f2a85-m/acpi/routing.asl
@@ -46,7 +46,7 @@
 		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
 		/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
 
-#if IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO)
+#if CONFIG(BOARD_ASUS_F2A85_M_PRO)
 		Package(){0x000FFFFF, 0, INTA, 0 },
 		Package(){0x000FFFFF, 1, INTB, 0 },
 		Package(){0x000FFFFF, 2, INTC, 0 },
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index e69564ea8e..dc20dc7dd8 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -167,7 +167,7 @@
 #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON	3
 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL	3
 
-#if IS_ENABLED(CONFIG_GFXUMA)
+#if CONFIG(GFXUMA)
 #define BLDCFG_UMA_ALIGNMENT                      UMA_4MB_ALIGNED
 #define BLDCFG_UMA_ALLOCATION_MODE		  UMA_SPECIFIED
 //#define BLDCFG_UMA_ALLOCATION_SIZE	  	  0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
index bed5a731cf..dffb726dc6 100644
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ b/src/mainboard/asus/f2a85-m/romstage.c
@@ -70,9 +70,9 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	u8 byte;
 	pci_devfn_t dev;
 
-	if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE))
+	if (CONFIG(POST_DEVICE_PCI_PCIE))
 		hudson_pci_port80();
-	else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC))
+	else if (CONFIG(POST_DEVICE_LPC))
 		hudson_lpc_port80();
 
 	/* enable SIO LPC decode */
@@ -95,7 +95,7 @@ void board_BeforeAgesa(struct sysinfo *cb)
 	/* enable SIO clock */
 	sbxxx_enable_48mhzout();
 
-	if (IS_ENABLED(CONFIG_BOARD_ASUS_F2A85_M_PRO))
+	if (CONFIG(BOARD_ASUS_F2A85_M_PRO))
 		superio_init_m_pro();
 	else
 		superio_init_m();
diff --git a/src/mainboard/asus/kcma-d8/acpi_tables.c b/src/mainboard/asus/kcma-d8/acpi_tables.c
index 52840cac6e..d705b213a2 100644
--- a/src/mainboard/asus/kcma-d8/acpi_tables.c
+++ b/src/mainboard/asus/kcma-d8/acpi_tables.c
@@ -31,7 +31,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 	/* create all subtables for processors */
 	current = acpi_create_madt_lapics(current);
 
-	if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
+	if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
 		apicid_sp5100 = 0x0;
 	else
 		apicid_sp5100 = 0x20;
@@ -70,7 +70,7 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current)
 	uint32_t apicid_sp5100;
 	uint32_t apicid_sr5650;
 
-	if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
+	if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
 		apicid_sp5100 = 0x0;
 	else
 		apicid_sp5100 = 0x20;
diff --git a/src/mainboard/asus/kcma-d8/bootblock.c b/src/mainboard/asus/kcma-d8/bootblock.c
index 6cfc93ca93..543ffed9c7 100644
--- a/src/mainboard/asus/kcma-d8/bootblock.c
+++ b/src/mainboard/asus/kcma-d8/bootblock.c
@@ -33,7 +33,7 @@ void bootblock_mainboard_init(void)
 	pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte);
 	recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1));
 	if (recovery_enabled) {
-#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
+#if CONFIG(USE_OPTION_TABLE)
 		/* Clear NVRAM checksum */
 		for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
 			cmos_write(0x0, addr);
diff --git a/src/mainboard/asus/kcma-d8/mptable.c b/src/mainboard/asus/kcma-d8/mptable.c
index 1abca65407..c9b83a0070 100644
--- a/src/mainboard/asus/kcma-d8/mptable.c
+++ b/src/mainboard/asus/kcma-d8/mptable.c
@@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v)
 
 	smp_write_processors(mc);
 
-	if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
+	if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
 		apicid_sp5100 = 0x0;
 	else
 		apicid_sp5100 = 0x20;
diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c
index 028af4c938..a74c6dd45c 100644
--- a/src/mainboard/asus/kcma-d8/romstage.c
+++ b/src/mainboard/asus/kcma-d8/romstage.c
@@ -464,7 +464,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sr5650_early_setup();
 	sb7xx_51xx_early_setup();
 
-	if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
+	if (CONFIG(LOGICAL_CPUS)) {
 		/* Core0 on each node is configured. Now setup any additional cores. */
 		printk(BIOS_DEBUG, "start_other_cores()\n");
 		start_other_cores(bsp_apicid);
@@ -472,7 +472,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		wait_all_other_cores_started(bsp_apicid);
 	}
 
-	if (IS_ENABLED(CONFIG_SET_FIDVID)) {
+	if (CONFIG(SET_FIDVID)) {
 		msr = rdmsr(MSR_COFVID_STS);
 		printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 
@@ -481,7 +481,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 		post_code(0x39);
 
-		#if IS_ENABLED(CONFIG_SET_FIDVID)
+		#if CONFIG(SET_FIDVID)
 		if (!warm_reset_detect(0)) {			// BSP is node 0
 			init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 		} else {
@@ -526,7 +526,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x3B);
 
 	/* Wait for all APs to be stopped, otherwise RAM initialization may hang */
-	if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+	if (CONFIG(LOGICAL_CPUS))
 		wait_all_other_cores_stopped(bsp_apicid);
 
 	/* It's the time to set ctrl in sysinfo now; */
@@ -540,9 +540,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #if 0
 	/* FIXME
 	 * After the AMD K10 code has been converted to use
-	 * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block
+	 * CONFIG(DEBUG_SMBUS) uncomment this block
 	 */
-	if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {
+	if (CONFIG(DEBUG_SMBUS)) {
 	        dump_spd_registers(&cpu[0]);
 		dump_smbus_registers();
 	}
diff --git a/src/mainboard/asus/kfsn4-dre/acpi_tables.c b/src/mainboard/asus/kfsn4-dre/acpi_tables.c
index ce3d4178da..587e2ff852 100644
--- a/src/mainboard/asus/kfsn4-dre/acpi_tables.c
+++ b/src/mainboard/asus/kfsn4-dre/acpi_tables.c
@@ -48,7 +48,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 		CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0);
 
 	/* Initialize interrupt mapping if mptable.c didn't. */
-	if (!IS_ENABLED(CONFIG_GENERATE_MP_TABLE)) {
+	if (!CONFIG(GENERATE_MP_TABLE)) {
 		/* Copied from mptable.c */
 		/* Enable interrupts for commonly used devices (USB, SATA, etc.) */
 		pci_write_config32(dev, 0x7c, 0x0d800018);
diff --git a/src/mainboard/asus/kfsn4-dre/bootblock.c b/src/mainboard/asus/kfsn4-dre/bootblock.c
index 796ca1a64e..fd57538afa 100644
--- a/src/mainboard/asus/kfsn4-dre/bootblock.c
+++ b/src/mainboard/asus/kfsn4-dre/bootblock.c
@@ -64,7 +64,7 @@ void bootblock_mainboard_init(void)
 
 	recovery_enabled = bootblock_read_recovery_jumper(GPIO_DEV);
 	if (recovery_enabled) {
-#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
+#if CONFIG(USE_OPTION_TABLE)
 		/* Clear NVRAM checksum */
 		for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
 			cmos_write(0x0, addr);
diff --git a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c
index 82172e82d5..bb51ada9e0 100644
--- a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c
+++ b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c
@@ -74,7 +74,7 @@ void get_bus_conf(void)
 		}
 	}
 
-	if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
+	if (CONFIG(LOGICAL_CPUS)) {
 		apicid_base = get_apicid_base(1);
 		printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 1: apicid_base: %08x\n", apicid_base);
 	}
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
index f6faf17152..6ac33f2ccd 100644
--- a/src/mainboard/asus/kfsn4-dre/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre/romstage.c
@@ -251,7 +251,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 */
 	wait_all_core0_started();
 
-	if (IS_ENABLED(CONFIG_SET_FIDVID)) {
+	if (CONFIG(SET_FIDVID)) {
 		msr = rdmsr(MSR_COFVID_STS);
 		printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 
@@ -270,7 +270,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 	}
 
-	if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
+	if (CONFIG(LOGICAL_CPUS)) {
 		/* Core0 on each node is configured. Now setup any additional cores. */
 		printk(BIOS_DEBUG, "start_other_cores()\n");
 		start_other_cores(bsp_apicid);
@@ -311,9 +311,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #if 0
 	/* FIXME
 	 * After the AMD K10 code has been converted to use
-	 * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block
+	 * CONFIG(DEBUG_SMBUS) uncomment this block
 	 */
-	if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {
+	if (CONFIG(DEBUG_SMBUS)) {
 		dump_spd_registers(&cpu[0]);
 		dump_smbus_registers();
 	}
diff --git a/src/mainboard/asus/kgpe-d16/acpi_tables.c b/src/mainboard/asus/kgpe-d16/acpi_tables.c
index 52840cac6e..d705b213a2 100644
--- a/src/mainboard/asus/kgpe-d16/acpi_tables.c
+++ b/src/mainboard/asus/kgpe-d16/acpi_tables.c
@@ -31,7 +31,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 	/* create all subtables for processors */
 	current = acpi_create_madt_lapics(current);
 
-	if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
+	if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
 		apicid_sp5100 = 0x0;
 	else
 		apicid_sp5100 = 0x20;
@@ -70,7 +70,7 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current)
 	uint32_t apicid_sp5100;
 	uint32_t apicid_sr5650;
 
-	if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
+	if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
 		apicid_sp5100 = 0x0;
 	else
 		apicid_sp5100 = 0x20;
diff --git a/src/mainboard/asus/kgpe-d16/bootblock.c b/src/mainboard/asus/kgpe-d16/bootblock.c
index 6cfc93ca93..543ffed9c7 100644
--- a/src/mainboard/asus/kgpe-d16/bootblock.c
+++ b/src/mainboard/asus/kgpe-d16/bootblock.c
@@ -33,7 +33,7 @@ void bootblock_mainboard_init(void)
 	pci_io_write_config8(PCI_DEV(0, 0x14, 0), 0x56, byte);
 	recovery_enabled = (!(pci_io_read_config8(PCI_DEV(0, 0x14, 0), 0x57) & 0x1));
 	if (recovery_enabled) {
-#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
+#if CONFIG(USE_OPTION_TABLE)
 		/* Clear NVRAM checksum */
 		for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
 			cmos_write(0x0, addr);
diff --git a/src/mainboard/asus/kgpe-d16/mptable.c b/src/mainboard/asus/kgpe-d16/mptable.c
index 15d0f500d6..ed01b548db 100644
--- a/src/mainboard/asus/kgpe-d16/mptable.c
+++ b/src/mainboard/asus/kgpe-d16/mptable.c
@@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v)
 
 	smp_write_processors(mc);
 
-	if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
+	if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
 		apicid_sp5100 = 0x0;
 	else
 		apicid_sp5100 = 0x20;
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index 7e823474e0..7fe9b640ad 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -575,7 +575,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	sr5650_early_setup();
 	sb7xx_51xx_early_setup();
 
-	if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
+	if (CONFIG(LOGICAL_CPUS)) {
 		/* Core0 on each node is configured. Now setup any additional cores. */
 		printk(BIOS_DEBUG, "start_other_cores()\n");
 		start_other_cores(bsp_apicid);
@@ -583,7 +583,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		wait_all_other_cores_started(bsp_apicid);
 	}
 
-	if (IS_ENABLED(CONFIG_SET_FIDVID)) {
+	if (CONFIG(SET_FIDVID)) {
 		msr = rdmsr(MSR_COFVID_STS);
 		printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 
@@ -592,7 +592,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 		post_code(0x39);
 
-		#if IS_ENABLED(CONFIG_SET_FIDVID)
+		#if CONFIG(SET_FIDVID)
 		if (!warm_reset_detect(0)) {			// BSP is node 0
 			init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 		} else {
@@ -637,7 +637,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	post_code(0x3B);
 
 	/* Wait for all APs to be stopped, otherwise RAM initialization may hang */
-	if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+	if (CONFIG(LOGICAL_CPUS))
 		wait_all_other_cores_stopped(bsp_apicid);
 
 	/* It's the time to set ctrl in sysinfo now; */
@@ -651,9 +651,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #if 0
 	/* FIXME
 	 * After the AMD K10 code has been converted to use
-	 * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block
+	 * CONFIG(DEBUG_SMBUS) uncomment this block
 	 */
-	if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {
+	if (CONFIG(DEBUG_SMBUS)) {
 	        dump_spd_registers(&cpu[0]);
 		dump_smbus_registers();
 	}
diff --git a/src/mainboard/asus/m4a78-em/get_bus_conf.c b/src/mainboard/asus/m4a78-em/get_bus_conf.c
index ade9c79e00..cbf436bf6f 100644
--- a/src/mainboard/asus/m4a78-em/get_bus_conf.c
+++ b/src/mainboard/asus/m4a78-em/get_bus_conf.c
@@ -37,7 +37,7 @@ void get_bus_conf(void)
 	pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
 
 	/* I/O APICs:   APIC ID Version State   Address */
-	if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+	if (CONFIG(LOGICAL_CPUS))
 		apicid_base = get_apicid_base(1);
 	else
 		apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index ffe283c61a..08ca7150f0 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -133,7 +133,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 */
 	wait_all_core0_started();
 
- #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+ #if CONFIG(LOGICAL_CPUS)
 	/* Core0 on each node is configured. Now setup any additional cores. */
 	printk(BIOS_DEBUG, "start_other_cores()\n");
 	start_other_cores(bsp_apicid);
@@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_early_setup();
 	sb7xx_51xx_early_setup();
 
- #if IS_ENABLED(CONFIG_SET_FIDVID)
+ #if CONFIG(SET_FIDVID)
 	msr = rdmsr(MSR_COFVID_STS);
 	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 
diff --git a/src/mainboard/asus/m4a785-m/get_bus_conf.c b/src/mainboard/asus/m4a785-m/get_bus_conf.c
index ade9c79e00..cbf436bf6f 100644
--- a/src/mainboard/asus/m4a785-m/get_bus_conf.c
+++ b/src/mainboard/asus/m4a785-m/get_bus_conf.c
@@ -37,7 +37,7 @@ void get_bus_conf(void)
 	pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
 
 	/* I/O APICs:   APIC ID Version State   Address */
-	if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+	if (CONFIG(LOGICAL_CPUS))
 		apicid_base = get_apicid_base(1);
 	else
 		apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 3246bdd70a..a53dbecdb2 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -133,7 +133,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 */
 	wait_all_core0_started();
 
- #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+ #if CONFIG(LOGICAL_CPUS)
 	/* Core0 on each node is configured. Now setup any additional cores. */
 	printk(BIOS_DEBUG, "start_other_cores()\n");
 	start_other_cores(bsp_apicid);
@@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_early_setup();
 	sb7xx_51xx_early_setup();
 
- #if IS_ENABLED(CONFIG_SET_FIDVID)
+ #if CONFIG(SET_FIDVID)
 	msr = rdmsr(MSR_COFVID_STS);
 	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 
@@ -218,7 +218,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  */
 BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
 {
-#if !IS_ENABLED(CONFIG_BOARD_ASUS_M4A785TM)
+#if !CONFIG(BOARD_ASUS_M4A785TM)
 	static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
 	/* If the BUID was adjusted in early_ht we need to do the manual override */
 	if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c
index d21b500fa5..837cb138f8 100644
--- a/src/mainboard/asus/m5a88-v/get_bus_conf.c
+++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c
@@ -37,7 +37,7 @@ void get_bus_conf(void)
 	pirq_router_bus = (sysconf.pci1234[0] >> 16) & 0xff;
 
 	/* I/O APICs:   APIC ID Version State   Address */
-	if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
+	if (CONFIG(LOGICAL_CPUS))
 		apicid_base = get_apicid_base(1);
 	else
 		apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 899814feeb..42e5c12af9 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -138,7 +138,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	 */
 	wait_all_core0_started();
 
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
+#if CONFIG(LOGICAL_CPUS)
 	/* Core0 on each node is configured. Now setup any additional cores. */
 	printk(BIOS_DEBUG, "start_other_cores()\n");
 	start_other_cores(bsp_apicid);
@@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	rs780_early_setup();
 	sb800_early_setup();
 
-#if IS_ENABLED(CONFIG_SET_FIDVID)
+#if CONFIG(SET_FIDVID)
 	msr = rdmsr(MSR_COFVID_STS);
 	printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 	post_code(0x39);
diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c
index c59f38cd36..6295a53f1c 100644
--- a/src/mainboard/asus/p5qpl-am/romstage.c
+++ b/src/mainboard/asus/p5qpl-am/romstage.c
@@ -76,7 +76,7 @@ static int setup_sio_gpio(void)
 	pnp_enter_ext_func_mode(GPIO_DEV);
 	pnp_set_logical_device(GPIO_DEV);
 
-	if (IS_ENABLED(CONFIG_BOARD_ASUS_P5QPL_AM)) {
+	if (CONFIG(BOARD_ASUS_P5QPL_AM)) {
 		/*
 		 * P5QPL-AM:
 		 * BSEL0 -> not hooked up (not supported anyways)