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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-24 00:04:22 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-31 03:41:11 +0000
commit1740230ace3aeede3a7ee5cadd1e17744cda07b3 (patch)
treebf4e9f45d71fef44056ba901ac91fcbfb423a525 /src/mainboard/asus
parentf054a4bf3d6ce459d15c9375e4ca2390d04ffb68 (diff)
downloadcoreboot-1740230ace3aeede3a7ee5cadd1e17744cda07b3.tar.xz
Remove all AMD K8 boards
Platforms with LATE_CBMEM_INIT were agreed to be removed with 4.7 release late 2017. Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/asus')
-rw-r--r--src/mainboard/asus/a8n_e/Kconfig62
-rw-r--r--src/mainboard/asus/a8n_e/Kconfig.name2
-rw-r--r--src/mainboard/asus/a8n_e/acpi_tables.c71
-rw-r--r--src/mainboard/asus/a8n_e/board_info.txt7
-rw-r--r--src/mainboard/asus/a8n_e/cmos.default11
-rw-r--r--src/mainboard/asus/a8n_e/cmos.layout56
-rw-r--r--src/mainboard/asus/a8n_e/devicetree.cb121
-rw-r--r--src/mainboard/asus/a8n_e/dsdt.asl265
-rw-r--r--src/mainboard/asus/a8n_e/get_bus_conf.c116
-rw-r--r--src/mainboard/asus/a8n_e/irq_tables.c193
-rw-r--r--src/mainboard/asus/a8n_e/mptable.c123
-rw-r--r--src/mainboard/asus/a8n_e/romstage.c150
-rw-r--r--src/mainboard/asus/a8n_sli/Kconfig9
-rw-r--r--src/mainboard/asus/a8n_sli/Kconfig.name2
-rw-r--r--src/mainboard/asus/a8n_sli/board_info.txt7
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/Kconfig60
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/Kconfig.name2
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/acpi_tables.c65
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/board_info.txt6
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/cmos.layout52
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/devicetree.cb97
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/dsdt.asl194
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/mptable.c112
-rw-r--r--src/mainboard/asus/a8v-e_deluxe/romstage.c206
-rw-r--r--src/mainboard/asus/a8v-e_se/Kconfig60
-rw-r--r--src/mainboard/asus/a8v-e_se/Kconfig.name2
-rw-r--r--src/mainboard/asus/a8v-e_se/acpi_tables.c67
-rw-r--r--src/mainboard/asus/a8v-e_se/board_info.txt7
-rw-r--r--src/mainboard/asus/a8v-e_se/cmos.layout52
-rw-r--r--src/mainboard/asus/a8v-e_se/devicetree.cb97
-rw-r--r--src/mainboard/asus/a8v-e_se/dsdt.asl239
-rw-r--r--src/mainboard/asus/a8v-e_se/mptable.c112
-rw-r--r--src/mainboard/asus/a8v-e_se/romstage.c206
-rw-r--r--src/mainboard/asus/k8v-x/Kconfig69
-rw-r--r--src/mainboard/asus/k8v-x/Kconfig.name2
-rw-r--r--src/mainboard/asus/k8v-x/acpi_tables.c67
-rw-r--r--src/mainboard/asus/k8v-x/board_info.txt2
-rw-r--r--src/mainboard/asus/k8v-x/cmos.layout52
-rw-r--r--src/mainboard/asus/k8v-x/devicetree.cb113
-rw-r--r--src/mainboard/asus/k8v-x/dsdt.asl176
-rw-r--r--src/mainboard/asus/k8v-x/irq_tables.c146
-rw-r--r--src/mainboard/asus/k8v-x/mainboard.c55
-rw-r--r--src/mainboard/asus/k8v-x/mptable.c112
-rw-r--r--src/mainboard/asus/k8v-x/romstage.c182
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/Kconfig98
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/Kconfig.name2
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/acpi/pm_ctrl.asl241
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/acpi_tables.c80
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/board_info.txt6
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/bootblock.c81
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/cmos.default12
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/cmos.layout117
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/devicetree.cb197
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/dsdt.asl947
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c116
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/irq_tables.c180
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/mptable.c153
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/resourcemap.c280
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/romstage.c362
-rw-r--r--src/mainboard/asus/kfsn4-dre_k8/spd_notes.txt69
-rw-r--r--src/mainboard/asus/m2n-e/Kconfig77
-rw-r--r--src/mainboard/asus/m2n-e/Kconfig.name2
-rw-r--r--src/mainboard/asus/m2n-e/Makefile.inc17
-rw-r--r--src/mainboard/asus/m2n-e/board_info.txt7
-rw-r--r--src/mainboard/asus/m2n-e/cmos.layout68
-rw-r--r--src/mainboard/asus/m2n-e/devicetree.cb117
-rw-r--r--src/mainboard/asus/m2n-e/fanctl.c60
-rw-r--r--src/mainboard/asus/m2n-e/get_bus_conf.c114
-rw-r--r--src/mainboard/asus/m2n-e/hda_verb.c79
-rw-r--r--src/mainboard/asus/m2n-e/mptable.c102
-rw-r--r--src/mainboard/asus/m2n-e/resourcemap.c277
-rw-r--r--src/mainboard/asus/m2n-e/romstage.c177
-rw-r--r--src/mainboard/asus/m2v-mx_se/Kconfig70
-rw-r--r--src/mainboard/asus/m2v-mx_se/Kconfig.name2
-rw-r--r--src/mainboard/asus/m2v-mx_se/acpi_tables.c68
-rw-r--r--src/mainboard/asus/m2v-mx_se/board_info.txt7
-rw-r--r--src/mainboard/asus/m2v-mx_se/cmos.default11
-rw-r--r--src/mainboard/asus/m2v-mx_se/cmos.layout60
-rw-r--r--src/mainboard/asus/m2v-mx_se/devicetree.cb77
-rw-r--r--src/mainboard/asus/m2v-mx_se/dsdt.asl241
-rw-r--r--src/mainboard/asus/m2v-mx_se/romstage.c183
-rw-r--r--src/mainboard/asus/m2v/Kconfig67
-rw-r--r--src/mainboard/asus/m2v/Kconfig.name2
-rw-r--r--src/mainboard/asus/m2v/acpi_tables.c69
-rw-r--r--src/mainboard/asus/m2v/board_info.txt7
-rw-r--r--src/mainboard/asus/m2v/cmos.layout52
-rw-r--r--src/mainboard/asus/m2v/devicetree.cb75
-rw-r--r--src/mainboard/asus/m2v/dsdt.asl545
-rw-r--r--src/mainboard/asus/m2v/irq_tables.c87
-rw-r--r--src/mainboard/asus/m2v/mainboard.c51
-rw-r--r--src/mainboard/asus/m2v/mptable.c143
-rw-r--r--src/mainboard/asus/m2v/romstage.c279
92 files changed, 0 insertions, 9941 deletions
diff --git a/src/mainboard/asus/a8n_e/Kconfig b/src/mainboard/asus/a8n_e/Kconfig
deleted file mode 100644
index 1852ae45e0..0000000000
--- a/src/mainboard/asus/a8n_e/Kconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-if BOARD_ASUS_A8N_E || BOARD_ASUS_A8N_SLI
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_939
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_CK804
- select HT_CHAIN_DISTRIBUTE
- select SUPERIO_ITE_IT8712F
- select HAVE_OPTION_TABLE
- select HAVE_CMOS_DEFAULT
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select BOARD_ROMSIZE_KB_512
- select CK804_USE_NIC
- select CK804_USE_ACI
- select QRANK_DIMM_SUPPORT
- select HAVE_ACPI_TABLES
-
-config MAINBOARD_DIR
- string
- default asus/a8n_e
-
-config DCACHE_RAM_BASE
- hex
- default 0xcf000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x01000
-
-config APIC_ID_OFFSET
- hex
- default 0x0
-
-if BOARD_ASUS_A8N_E
-config MAINBOARD_PART_NUMBER
- string
- default "A8N-E"
-endif
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config IRQ_SLOT_COUNT
- int
- default 13
-
-endif # BOARD_ASUS_A8N_E
diff --git a/src/mainboard/asus/a8n_e/Kconfig.name b/src/mainboard/asus/a8n_e/Kconfig.name
deleted file mode 100644
index 02b00e7dd8..0000000000
--- a/src/mainboard/asus/a8n_e/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_A8N_E
- bool "A8N-E"
diff --git a/src/mainboard/asus/a8n_e/acpi_tables.c b/src/mainboard/asus/a8n_e/acpi_tables.c
deleted file mode 100644
index da90fd3ddf..0000000000
--- a/src/mainboard/asus/a8n_e/acpi_tables.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * ACPI support
- * written by Stefan Reinauer <stepan@openbios.org>
- * (C) 2005 Stefan Reinauer
- *
- * Copyright 2005 AMD
- * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include "../../../northbridge/amd/amdk8/acpi.h"
-
-/* APIC */
-unsigned long acpi_fill_madt(unsigned long current)
-{
- struct device *dev;
- struct resource *res;
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write NVIDIA CK804 IOAPIC. */
- dev = dev_find_slot(0x0, PCI_DEVFN(0x1,0));
- ASSERT(dev != NULL);
-
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- ASSERT(res != NULL);
-
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
- CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0);
-
- /* Initialize interrupt mapping if mptable.c didn't. */
-#if (!CONFIG_GENERATE_MP_TABLE)
-#error untested config
- pci_write_config32(dev, 0x7c, 0x0120d218);
- pci_write_config32(dev, 0x80, 0x12008a00);
- pci_write_config32(dev, 0x84, 0x0000007d);
-#endif
-
- /* IRQ of timer */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- /* IRQ9 */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* create all subtables for processors */
- /* acpi_create_madt_lapic_nmis returns current, not size. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/asus/a8n_e/board_info.txt b/src/mainboard/asus/a8n_e/board_info.txt
deleted file mode 100644
index 2e3e6424e0..0000000000
--- a/src/mainboard/asus/a8n_e/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: desktop
-Board URL: http://www.asus.com/Motherboards/AMD_Socket_939/A8NE/
-ROM package: PLCC
-ROM protocol: LPC
-ROM socketed: y
-Flashrom support: y
-Release year: 2005
diff --git a/src/mainboard/asus/a8n_e/cmos.default b/src/mainboard/asus/a8n_e/cmos.default
deleted file mode 100644
index 84dd0274af..0000000000
--- a/src/mainboard/asus/a8n_e/cmos.default
+++ /dev/null
@@ -1,11 +0,0 @@
-boot_option=Fallback
-debug_level=Spew
-power_on_after_fail=Enable
-ECC_memory=Disable
-hw_scrubber=Enable
-interleave_chip_selects=Enable
-max_mem_clock=DDR400
-multi_core=Enable
-slow_cpu=off
-nmi=Enable
-iommu=Enable
diff --git a/src/mainboard/asus/a8n_e/cmos.layout b/src/mainboard/asus/a8n_e/cmos.layout
deleted file mode 100644
index dc2977b250..0000000000
--- a/src/mainboard/asus/a8n_e/cmos.layout
+++ /dev/null
@@ -1,56 +0,0 @@
-entries
- 0 384 r 0 reserved_memory
- 384 1 e 4 boot_option
- 386 1 e 1 ECC_memory
- 388 4 h 0 reboot_counter
-# 392 3 r 0 unused
- 395 1 e 1 hw_scrubber
- 396 1 e 1 interleave_chip_selects
- 397 2 e 8 max_mem_clock
- 399 1 e 2 multi_core
- 400 1 e 1 power_on_after_fail
- 412 4 e 6 debug_level
- 440 4 e 9 slow_cpu
- 444 1 e 1 nmi
- 445 1 e 1 iommu
- 728 256 h 0 user_data
- 984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
- 1000 24 r 0 reserved_memory1
-
-enumerations
-
-#ID value text
- 1 0 Disable
- 1 1 Enable
- 2 0 Enable
- 2 1 Disable
- 4 0 Fallback
- 4 1 Normal
-
- 6 5 Notice
- 6 6 Info
- 6 7 Debug
- 6 8 Spew
- 7 0 Network
- 7 1 HDD
- 7 2 Floppy
- 7 8 Fallback_Network
- 7 9 Fallback_HDD
- 7 10 Fallback_Floppy
- 8 0 DDR400
- 8 1 DDR333
- 8 2 DDR266
- 8 3 DDR200
- 9 0 off
- 9 1 87.5 %
- 9 2 75.0 %
- 9 3 62.5 %
- 9 4 50.0 %
- 9 5 37.5 %
- 9 6 25.0 %
- 9 7 12.5 %
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/a8n_e/devicetree.cb b/src/mainboard/asus/a8n_e/devicetree.cb
deleted file mode 100644
index bbbfeb89f2..0000000000
--- a/src/mainboard/asus/a8n_e/devicetree.cb
+++ /dev/null
@@ -1,121 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_939 # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
-
- device domain 0 on # PCI domain
- subsystemid 0x1043 0x815a inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on # Link 0 == LDT 0
- chip southbridge/nvidia/ck804 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/ite/it8712f # Super I/O
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 off # Com2 (N/A on this board)
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.4 on # Environment controller
- io 0x60 = 0x290
- io 0x62 = 0x0000
- irq 0x70 = 0x00
- end
- device pnp 2e.5 on # PS/2 keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x71 = 2
- end
- device pnp 2e.6 on # PS/2 mouse
- irq 0x70 = 12
- irq 0x71 = 2
- end
- device pnp 2e.7 on # GPIO config
- io 0x60 = 0x0800
- io 0x62 = 0x0808
- io 0x64 = 0x0810
- # Set GPIO 1 & 2
- io 0x25 = 0x0000
- # Set GPIO 3 & 4
- io 0x27 = 0x2540
- # GPIO Polarity for Set 3
- io 0xb2 = 0x2100
- # GPIO Pin Internal Pull up for Set 3
- io 0xba = 0x0100
- # Simple I/O register config
- io 0xc0 = 0x0000
- io 0xc2 = 0x2540
- io 0xc8 = 0x0000
- io 0xca = 0x0500
- end
- device pnp 2e.8 on # MIDI port
- io 0x60 = 0x300
- irq 0x70 = 10
- end
- device pnp 2e.9 on # Game port
- io 0x60 = 0x201
- end
- device pnp 2e.a off # IR (N/A on this board)
- io 0x60 = 0x310
- irq 0x70 = 11
- end
- end
- end
- device pci 1.1 on # SM 0
- # chip drivers/generic/generic # DIMM 0-0-0
- # device i2c 50 on end
- # end
- # chip drivers/generic/generic # DIMM 0-0-1
- # device i2c 51 on end
- # end
- # chip drivers/generic/generic # DIMM 0-1-0
- # device i2c 52 on end
- # end
- # chip drivers/generic/generic # DIMM 0-1-1
- # device i2c 53 on end
- # end
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # Onboard audio (ACI)
- device pci 4.1 off end # Onboard modem (MCI), N/A
- device pci 6.0 on end # IDE
- device pci 7.0 on end # SATA 1
- device pci 8.0 on end # SATA 0
- device pci 9.0 on end # PCI
- device pci a.0 on end # NIC
- device pci b.0 on end # PCI E 3
- device pci c.0 on end # PCI E 2
- device pci d.0 on end # PCI E 1
- device pci e.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- # TODO
- # register "mac_eeprom_smbus" = "3"
- # register "mac_eeprom_addr" = "0x51"
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/asus/a8n_e/dsdt.asl b/src/mainboard/asus/a8n_e/dsdt.asl
deleted file mode 100644
index 45aeaf1c21..0000000000
--- a/src/mainboard/asus/a8n_e/dsdt.asl
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "CB-DSDT ", 1)
-{
- #include "northbridge/amd/amdk8/util.asl"
-
- /* For now only define 2 power states:
- * - S0 which is fully on
- * - S5 which is soft off
- * Any others would involve declaring the wake up methods.
- */
- Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
- Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 })
-
- Name (PICM, 0x00)
- Method (_PIC, 1, Serialized) {
- Store (Arg0, PICM)
- }
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device (CK804) */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- \_SB.GXXX(node, link)
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
-#include "southbridge/nvidia/ck804/acpi/ck804.asl"
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LLAS, 0x00 },//APCS
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LLAS, 0x00 },//APCS
- Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LUOH, 0x00 },//APCF
- Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LUEH, 0x00 },//APCL
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LAUD, 0x00 },//APCJ
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LMOD, 0x00 },//APCK
- Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI0.LPA0, 0x00 },//APCZ
- Package (0x04) { 0x0007FFFF, 0x00, \_SB.PCI0.LSA0, 0x00 },//APSI
- Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LSA1, 0x00 },//APSJ
-
- Package (0x04) { 0x0009FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0009FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0009FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0009FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
-
- Package (0x04) { 0x000AFFFF, 0x00, \_SB.PCI0.LEMA, 0x00 },//APCH
-
- Package (0x04) { 0x000BFFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//APC2
- Package (0x04) { 0x000BFFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },//APC3
- Package (0x04) { 0x000BFFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },//APC4
- Package (0x04) { 0x000BFFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },//APC1
-
- Package (0x04) { 0x000CFFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//APC1
- Package (0x04) { 0x000CFFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },//APC2
- Package (0x04) { 0x000CFFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },//APC3
- Package (0x04) { 0x000CFFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },//APC4
-
- Package (0x04) { 0x000DFFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },//APC4
- Package (0x04) { 0x000DFFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },//APC1
- Package (0x04) { 0x000DFFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },//APC2
- Package (0x04) { 0x000DFFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },//APC3
-
- Package (0x04) { 0x000EFFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//APC3
- Package (0x04) { 0x000EFFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },//APC4
- Package (0x04) { 0x000EFFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },//APC1
- Package (0x04) { 0x000EFFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },//APC2
- })
-
- Device (PCIC)
- {
- Name (_ADR, 0x00090000)
- Name (_UID, 0x00)
- Name (_PRT, Package () {
- /* AGR slot */
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
- })
- }
-
- /* 2:00 PCIe x1 */
- Device (PEX1)
- {
- Name (_ADR, 0x000d0000)
- Name (_UID, 0x00)
- }
-
- /* 3:00 PCIe x16 */
- Device (PEX0)
- {
- Name (_ADR, 0x000e0000)
- Name (_UID, 0x00)
- }
-
- Device (LPC) {
- Name (_HID, EisaId ("PNP0A05"))
- Name (_ADR, 0x00010000)
-
- OperationRegion (CF44, PCI_Config, 0x44, 0x04)
- Field (CF44, ByteAcc, NoLock, Preserve)
- {
- ETBA, 32,
- }
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
- /* Parallel port */
- Device (LP0)
- {
- Name (_HID, EisaId ("PNP0400")) // "PNP0401" for ECP
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- FixedIO (0x0378, 0x10)
- IRQNoFlags () {7}
- })
- Return (TMP)
- }
- }
-
- /* Floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () {
- FixedIO (0x03F0, 0x08)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
-#if 0
- Device (HPET)
- {
- Name (_HID, EisaId ("PNP0103"))
- Name (CRS, ResourceTemplate ()
- {
- Memory32Fixed (ReadOnly,
- 0x00000000,
- 0x00001000,
- _Y02)
- })
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0F)
- }
- Method (_CRS, 0, NotSerialized)
- {
- CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT)
- Store (ETBA, HPT)
- Return (CRS)
- }
-
- }
-#endif
- }
- }
- }
-}
diff --git a/src/mainboard/asus/a8n_e/get_bus_conf.c b/src/mainboard/asus/a8n_e/get_bus_conf.c
deleted file mode 100644
index b1e94d8896..0000000000
--- a/src/mainboard/asus/a8n_e/get_bus_conf.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <cpu/amd/multicore.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include <stdlib.h>
-
-/*
- * Global variables for MB layouts and these will be shared by irqtable,
- * mptable and acpi_tables.
- */
-/* busnum is default */
-unsigned char bus_ck804[6];
-unsigned apicid_ck804;
-
-/*
- * Here you only need to set value in pci1234 for HT-IO that could be installed
- * or not. You may need to preset pci1234 for HT-IO board, please refer to
- * src/northbridge/amd/amdk8/get_sblk_pci1234.c for details.
- */
-unsigned pci1234x[] = {
- 0x0000ff0, /* No HTIO for A8N-E */
-};
-
-/*
- * HT Chain device num, actually it is unit id base of every ht device in
- * chain, assume every chain only have 4 ht device at most.
- */
-unsigned hcdnx[] = {
- 0x20202020, /* A8N-E has only one ht-chain */
-};
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
- unsigned apicid_base, sbdn;
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; /* Do it only once. */
-
- get_bus_conf_done = 1;
-
- /* FIXME: Is this really needed twice? */
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
- sbdn = sysconf.sbdn;
-
- for (i = 0; i < 6; i++)
- bus_ck804[i] = 0;
-
- bus_ck804[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-
- /* CK804 */
- dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x09, 0));
- if (dev) {
- bus_ck804[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804[2]++;
- } else {
- printk
- (BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x09);
- bus_ck804[1] = 2;
- bus_ck804[2] = 3;
- }
-
- for (i = 2; i < 6; i++) {
- dev = dev_find_slot(bus_ck804[0],
- PCI_DEVFN(sbdn + 0x0b + i - 2, 0));
- if (dev) {
- bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_ck804[0], sbdn + 0x0b + i - 2);
- }
- }
-
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(3);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_ck804 = apicid_base + 0;
-}
diff --git a/src/mainboard/asus/a8n_e/irq_tables.c b/src/mainboard/asus/a8n_e/irq_tables.c
deleted file mode 100644
index 59d506df01..0000000000
--- a/src/mainboard/asus/a8n_e/irq_tables.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_isa;
-extern unsigned char bus_ck804[6];
-
-
-/**
- * Add one line to IRQ table.
- */
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-/**
- * Create the IRQ routing table.
- * Values are derived from getpir generated code.
- */
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num, sbdn;
- uint8_t *v, sum = 0;
- int i;
-
- /* get_bus_conf() will find out all bus num and APIC that share with
- * mptable.c and mptable.c.
- */
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000. */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *)(addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
- pirq->rtr_bus = bus_ck804[0];
- pirq->rtr_devfn = ((sbdn + 9) << 3) | 0;
- pirq->exclusive_irqs = 0x828;
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x005c;
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* Slot1 PCIE 16x */
- write_pirq_info(pirq_info, bus_ck804[1], (0 << 3) | 0, 0x3, 0xdeb8, 0x4,
- 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0);
- pirq_info++;
- slot_num++;
-
- /* Slot2 PCIE 1x */
- write_pirq_info(pirq_info, bus_ck804[2], (0 << 3) | 0, 0x4, 0xdeb8, 0x1,
- 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0);
- pirq_info++;
- slot_num++;
-
- /* Slot3 PCIE 1x */
- write_pirq_info(pirq_info, bus_ck804[3], (0 << 3) | 0, 0x1, 0xdeb8, 0x2,
- 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0);
- pirq_info++;
- slot_num++;
-
- /* Slot4 PCIE 4x */
- write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0, 0x2,
- 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 7, 0);
- pirq_info++;
- slot_num++;
-
- /* Slot5 - Slot7 PCI */
- for (i = 0; i < 3; i++) {
- write_pirq_info(pirq_info, bus_ck804[5], (0 << (6 + i)) | 0,
- ((i + 0) % 4) + 1, 0xdeb8,
- ((i + 1) % 4) + 1, 0xdeb8,
- ((i + 2) % 4) + 1, 0xdeb8,
- ((i + 3) % 4) + 1, 0xdeb8, i, 0);
- pirq_info++;
- slot_num++;
- }
-
- /* PCI bridge */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 9) << 3) | 0, 0x1,
- 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* SMBus */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 1) << 3) | 0, 0x2,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* USB */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 2) << 3) | 0, 0x1,
- 0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* Audio */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 4) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* SATA */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 7) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* SATA */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 8) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* NIC */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 0xa) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
-#if 0
- /* Firewire? */
- write_pirq_info(pirq_info, bus_ck804_1, (0x5 << 3) | 0, 0x3, 0xdeb8, 0,
- 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-#endif
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum)
- pirq->checksum = sum;
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c
deleted file mode 100644
index 40a06a4c77..0000000000
--- a/src/mainboard/asus/a8n_e/mptable.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_ck804[6];
-extern unsigned apicid_ck804;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- unsigned sbdn;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- {
- struct device *dev;
- struct resource *res;
- uint32_t dword;
-
- dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11,
- res2mmio(res, 0, 0));
- }
-
- /* Initialize interrupt mapping. */
- dword = 0x01200000;
- pci_write_config32(dev, 0x7c, dword);
-
- dword = 0x12008009;
- pci_write_config32(dev, 0x80, dword);
-
- dword = 0x0002010d;
- pci_write_config32(dev, 0x84, dword);
-
- }
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
-
- // Onboard ck804 smbus
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804,
- 0xa);
-
- // Onboard ck804 USB 1.1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804,
- 0x15);
-
- // Onboard ck804 USB 2
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804,
- 0x14);
-
- /* Onboard audio */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 4) << 2) | 0, apicid_ck804, 0x3);
-
- // Onboard ck804 SATA 0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804,
- 0x17);
-
- // Onboard ck804 SATA 1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804,
- 0x16);
-
- // Onboard ck804 NIC
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 10) << 2) | 0, apicid_ck804,
- 0x17);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, bus_ck804[0]);
-
- /* There is no extension information... */
-
- /* Compute the checksums. */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
deleted file mode 100644
index e4ed339924..0000000000
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Used by ite_enable_serial(). */
-#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
-#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <cpu/x86/lapic.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8712f/it8712f.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <console/console.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include <southbridge/nvidia/ck804/early_smbus.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <spd.h>
-#include <northbridge/amd/amdk8/pre_f.h>
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "lib/generic_sdram.c"
-#include <southbridge/nvidia/ck804/early_setup_ss.h>
-#include "southbridge/nvidia/ck804/early_setup.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-static void sio_setup(void)
-{
- uint32_t dword;
- uint8_t byte;
-
- /* Subject decoding */
- byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
-
- /* LPC Positive Decode 0 */
- dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
- dword |= (1 << 0) | (1 << 1); /* Serial 0, Serial 1 */
- pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
-#endif
- };
-
- int needs_reset;
- unsigned nodes, bsp_apicid = 0;
- struct mem_controller ctrl[8];
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx);
-
- ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
-#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 0));
-#endif
-
- needs_reset = setup_coherent_ht_domain();
-
- wait_all_core0_started();
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched. */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- needs_reset |= ht_setup_chains_x();
- needs_reset |= ck804_early_setup_x();
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- nodes = get_nodes();
- /* It's the time to set ctrl now. */
- fill_mem_ctrl(nodes, ctrl, spd_addr);
-
- enable_smbus();
-
-#if 0
- dump_spd_registers(&ctrl[0]);
- dump_smbus_registers();
-#endif
-
- sdram_initialize(nodes, ctrl);
-
-#if 0
- print_pci_devices();
- dump_pci_devices();
-#endif
-}
diff --git a/src/mainboard/asus/a8n_sli/Kconfig b/src/mainboard/asus/a8n_sli/Kconfig
deleted file mode 100644
index e2ac03dea5..0000000000
--- a/src/mainboard/asus/a8n_sli/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-if BOARD_ASUS_A8N_SLI
-
-# Dummy for abuild
-
-config MAINBOARD_PART_NUMBER
- string
- default "A8N-SLI"
-
-endif
diff --git a/src/mainboard/asus/a8n_sli/Kconfig.name b/src/mainboard/asus/a8n_sli/Kconfig.name
deleted file mode 100644
index 700bdc291a..0000000000
--- a/src/mainboard/asus/a8n_sli/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_A8N_SLI
- bool "A8N-SLI"
diff --git a/src/mainboard/asus/a8n_sli/board_info.txt b/src/mainboard/asus/a8n_sli/board_info.txt
deleted file mode 100644
index e9b47eb220..0000000000
--- a/src/mainboard/asus/a8n_sli/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Board URL: http://www.asus.com/Motherboards/AMD_Socket_939/A8NSLI/
-Category: desktop
-ROM package: PLCC
-ROM socketed: y
-Flashrom support: y
-Clone of: asus/a8n_e
-Release year: 2005
diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig b/src/mainboard/asus/a8v-e_deluxe/Kconfig
deleted file mode 100644
index b067047ae1..0000000000
--- a/src/mainboard/asus/a8v-e_deluxe/Kconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-if BOARD_ASUS_A8V_E_DELUXE
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_939
- select K8_HT_FREQ_1G_SUPPORT
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_VIA_VT8237R
- select SOUTHBRIDGE_VIA_K8T890
- select SOUTHBRIDGE_VIA_SUBTYPE_K8T890
- select SUPERIO_WINBOND_W83627EHG
- select HAVE_OPTION_TABLE
- select HAVE_ACPI_TABLES
- select HAVE_MP_TABLE
- select BOARD_ROMSIZE_KB_512
- select RAMINIT_SYSINFO
- select QRANK_DIMM_SUPPORT
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default asus/a8v-e_deluxe
-
-config DCACHE_RAM_BASE
- hex
- default 0xcc000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x4000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MAINBOARD_PART_NUMBER
- string
- default "A8V-E Deluxe"
-
-config HW_MEM_HOLE_SIZEK
- hex
- default 0x0
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-endif # BOARD_ASUS_A8V_E_DELUXE
diff --git a/src/mainboard/asus/a8v-e_deluxe/Kconfig.name b/src/mainboard/asus/a8v-e_deluxe/Kconfig.name
deleted file mode 100644
index c55a1dd02e..0000000000
--- a/src/mainboard/asus/a8v-e_deluxe/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_A8V_E_DELUXE
- bool "A8V-E Deluxe"
diff --git a/src/mainboard/asus/a8v-e_deluxe/acpi_tables.c b/src/mainboard/asus/a8v-e_deluxe/acpi_tables.c
deleted file mode 100644
index 01382ede39..0000000000
--- a/src/mainboard/asus/a8v-e_deluxe/acpi_tables.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Written by Stefan Reinauer <stepan@openbios.org>.
- * ACPI FADT, FACS, and DSDT table support added by
- *
- * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
- * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/device.h>
-#include <device/pci_ids.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
-#include <cpu/amd/amdk8_sysconf.h>
-
-void get_bus_conf(void)
-{
- /* FIXME: implement this. */
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int gsi_base = 0x18;
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- VT8237R_APIC_ID, IO_APIC_ADDR, 0);
-
- /* Write NB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
-
- /* IRQ9 ACPI active low. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* IRQ0 -> APIC IRQ2. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0x0);
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/asus/a8v-e_deluxe/board_info.txt b/src/mainboard/asus/a8v-e_deluxe/board_info.txt
deleted file mode 100644
index 497c8e9dfb..0000000000
--- a/src/mainboard/asus/a8v-e_deluxe/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Category: desktop
-Board URL: http://www.asus.com/Motherboards/AMD_Socket_939/A8VE_Deluxe/
-ROM package: PLCC
-ROM socketed: y
-Flashrom support: y
-Release year: 2005
diff --git a/src/mainboard/asus/a8v-e_deluxe/cmos.layout b/src/mainboard/asus/a8v-e_deluxe/cmos.layout
deleted file mode 100644
index aae7ceb075..0000000000
--- a/src/mainboard/asus/a8v-e_deluxe/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/a8v-e_deluxe/devicetree.cb b/src/mainboard/asus/a8v-e_deluxe/devicetree.cb
deleted file mode 100644
index 5e56acca0a..0000000000
--- a/src/mainboard/asus/a8v-e_deluxe/devicetree.cb
+++ /dev/null
@@ -1,97 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # APIC cluster
- chip cpu/amd/socket_939 # CPU
- device lapic 0 on end # APIC
- end
- end
- device domain 0 on # PCI domain
- subsystemid 1043 0 inherit
- chip northbridge/amd/amdk8 # mc0
- device pci 18.0 on # Northbridge
- # Devices on link 0, link 0 == LDT 0
- chip southbridge/via/vt8237r # Southbridge
- register "ide0_enable" = "1" # Enable IDE channel 0
- register "ide1_enable" = "1" # Enable IDE channel 1
- register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
- register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
- register "fn_ctrl_lo" = "0" # Enable SB functions
- register "fn_ctrl_hi" = "0xad" # Enable SB functions
- device pci 0.0 on end # HT
- device pci f.1 on end # IDE
- device pci 11.0 on # LPC
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- chip superio/winbond/w83627ehg # Super I/O
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2 (N/A on this board)
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 off # PS/2 keyboard & mouse (off)
- end
- device pnp 2e.106 off # Serial flash interface (SFI)
- io 0x60 = 0x100
- end
- device pnp 2e.007 off # GPIO 1
- end
- device pnp 2e.107 on # Game port
- io 0x60 = 0x201
- end
- device pnp 2e.207 on # MIDI
- io 0x62 = 0x330
- irq 0x70 = 0xa
- end
- device pnp 2e.307 off # GPIO 6
- end
- device pnp 2e.8 off # WDTO#, PLED
- end
- device pnp 2e.009 on # GPIO 2
- end
- device pnp 2e.109 off # GPIO 3
- end
- device pnp 2e.209 off # GPIO 4
- end
- device pnp 2e.309 on # GPIO 5
- end
- device pnp 2e.a off # ACPI
- end
- device pnp 2e.b on # Hardware monitor
- io 0x60 = 0x290
- irq 0x70 = 0
- end
- end
- end
- device pci 12.0 off end # VIA LAN (off, other chip used)
- end
- chip southbridge/via/k8t890 # "Southbridge" K8T890
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/asus/a8v-e_deluxe/dsdt.asl b/src/mainboard/asus/a8v-e_deluxe/dsdt.asl
deleted file mode 100644
index 06cc76accd..0000000000
--- a/src/mainboard/asus/a8v-e_deluxe/dsdt.asl
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1)
-{
- #include <southbridge/via/k8t890/acpi/sleepstates.asl>
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- /* PCI Routing Table */
- /* aaa */
- Name (_PRT, Package () {
- Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */
- Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },
- Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */
- Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },
- Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */
- Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
- Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */
- Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
- Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
- Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
- Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
- Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
- Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */
- })
-
- Device (PEGG)
- {
- Name (_ADR, 0x00020000)
- Name (_UID, 0x00)
- Name (_BBN, 0x02)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
- })
- }
-
- Device (PEX0)
- {
- Name (_ADR, 0x00030000)
- Name (_UID, 0x00)
- Name (_BBN, 0x03)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
- })
- }
-
- Device (PEX1)
- {
- Name (_ADR, 0x00030001)
- Name (_UID, 0x00)
- Name (_BBN, 0x04)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
- })
- }
-
- Device (PEX2)
- {
- Name (_ADR, 0x00030002)
- Name (_UID, 0x00)
- Name (_BBN, 0x05)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
- })
- }
-
- Device (PEX3)
- {
- Name (_ADR, 0x00030003)
- Name (_UID, 0x00)
- Name (_BBN, 0x06)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },
- })
- }
-
- Device (ISA) {
- Name (_ADR, 0x00110000)
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () {
- IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
- IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
- }
- }
- }
-}
diff --git a/src/mainboard/asus/a8v-e_deluxe/mptable.c b/src/mainboard/asus/a8v-e_deluxe/mptable.c
deleted file mode 100644
index f3d3d06207..0000000000
--- a/src/mainboard/asus/a8v-e_deluxe/mptable.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <stdint.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
- smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
-
- mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums. */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
deleted file mode 100644
index 5ade055bc8..0000000000
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2006 MSI
- * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-unsigned int get_sbdn(unsigned bus);
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <halt.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/early_ht.c"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627ehg/w83627ehg.h>
-#include <southbridge/via/vt8237r/vt8237r.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <spd.h>
-#include <northbridge/amd/amdk8/pre_f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
-#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <reset.h>
-void do_soft_reset(void)
-{
- uint8_t tmp;
-
- set_bios_reset();
- printk(BIOS_DEBUG, "soft reset\n");
-
- /* PCI reset */
- tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
- tmp |= 0x01;
- pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
-
- halt();
-}
-
-#include "southbridge/via/k8t890/early_car.c"
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
- return (dev >> 15) & 0x1f;
-}
-
-static void sio_init(void)
-{
- u8 reg;
-
- pnp_enter_conf_state(SERIAL_DEV);
- /* We have 24MHz input. */
- reg = pnp_read_config(SERIAL_DEV, 0x24);
- pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
- /* We have GPIO for KB/MS pin. */
- reg = pnp_read_config(SERIAL_DEV, 0x2a);
- pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
- /* We have all RESTOUT and even some reserved bits, too. */
- reg = pnp_read_config(SERIAL_DEV, 0x2c);
- pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
- pnp_exit_conf_state(SERIAL_DEV);
-
- pnp_enter_conf_state(ACPI_DEV);
- pnp_set_logical_device(ACPI_DEV);
- /*
- * Set the delay rising time from PWROK_LP to PWROK_ST to
- * 300 - 600ms, and 0 to vice versa.
- */
- reg = pnp_read_config(ACPI_DEV, 0xe6);
- pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
- /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
- reg = pnp_read_config(ACPI_DEV, 0xe4);
- pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
- pnp_exit_conf_state(ACPI_DEV);
-
- pnp_enter_conf_state(GPIO_DEV);
- pnp_set_logical_device(GPIO_DEV);
- /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
- pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */
- pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */
- pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */
- pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0 = output 1 = input */
- pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */
- pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */
- pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */
- pnp_exit_conf_state(GPIO_DEV);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
- unsigned bsp_apicid = 0;
- int needs_reset = 0;
- struct sys_info *sysinfo = &sysinfo_car;
-
- sio_init();
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- enable_rom_decode();
-
- printk(BIOS_INFO, "now booting... romstage\n");
-
- /* Is this a CPU only reset? Or is this a secondary CPU? */
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0. */
- /* Allow the HT devices to be found. */
- enumerate_ht_chain();
- }
-
- printk(BIOS_INFO, "now booting... real_main\n");
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- /* Halt if there was a built in self test failure. */
- report_bist_failure(bist);
-
- setup_default_resource_map();
- setup_coherent_ht_domain();
- wait_all_core0_started();
-
- printk(BIOS_INFO, "now booting... Core0 started\n");
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched. */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
- init_timer();
- ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- needs_reset |= k8t890_early_setup_ht();
-
- if (needs_reset) {
- printk(BIOS_DEBUG, "ht reset -\n");
- soft_reset();
- }
-
- /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
- enable_fid_change();
- init_fidvid_bsp(bsp_apicid);
-
- /* Stop the APs so we can start them later in init. */
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl now. */
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
diff --git a/src/mainboard/asus/a8v-e_se/Kconfig b/src/mainboard/asus/a8v-e_se/Kconfig
deleted file mode 100644
index 0188ff98b5..0000000000
--- a/src/mainboard/asus/a8v-e_se/Kconfig
+++ /dev/null
@@ -1,60 +0,0 @@
-if BOARD_ASUS_A8V_E_SE
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_939
- select K8_HT_FREQ_1G_SUPPORT
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_VIA_VT8237R
- select SOUTHBRIDGE_VIA_K8T890
- select SOUTHBRIDGE_VIA_SUBTYPE_K8T890
- select SUPERIO_WINBOND_W83627EHG
- select HAVE_OPTION_TABLE
- select HAVE_ACPI_TABLES
- select HAVE_MP_TABLE
- select BOARD_ROMSIZE_KB_512
- select RAMINIT_SYSINFO
- select QRANK_DIMM_SUPPORT
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default asus/a8v-e_se
-
-config DCACHE_RAM_BASE
- hex
- default 0xcc000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x4000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MAINBOARD_PART_NUMBER
- string
- default "A8V-E SE"
-
-config HW_MEM_HOLE_SIZEK
- hex
- default 0x0
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-endif # BOARD_ASUS_A8V_E_SE
diff --git a/src/mainboard/asus/a8v-e_se/Kconfig.name b/src/mainboard/asus/a8v-e_se/Kconfig.name
deleted file mode 100644
index 34afcd89c0..0000000000
--- a/src/mainboard/asus/a8v-e_se/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_A8V_E_SE
- bool "A8V-E SE"
diff --git a/src/mainboard/asus/a8v-e_se/acpi_tables.c b/src/mainboard/asus/a8v-e_se/acpi_tables.c
deleted file mode 100644
index ab9811a127..0000000000
--- a/src/mainboard/asus/a8v-e_se/acpi_tables.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Written by Stefan Reinauer <stepan@openbios.org>.
- * ACPI FADT, FACS, and DSDT table support added by
- *
- * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
- * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/device.h>
-#include <device/pci_ids.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
-#include "northbridge/amd/amdk8/acpi.h"
-#include <cpu/amd/powernow.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-void get_bus_conf(void)
-{
- /* FIXME: implement this. */
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int gsi_base = 0x18;
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- VT8237R_APIC_ID, IO_APIC_ADDR, 0);
-
- /* Write NB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
-
- /* IRQ9 ACPI active low. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* IRQ0 -> APIC IRQ2. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0x0);
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/asus/a8v-e_se/board_info.txt b/src/mainboard/asus/a8v-e_se/board_info.txt
deleted file mode 100644
index c08475a48b..0000000000
--- a/src/mainboard/asus/a8v-e_se/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: desktop
-Board URL: http://www.asus.com/Motherboards/AMD_Socket_939/A8VE_SE/
-ROM package: PLCC
-ROM protocol: LPC
-ROM socketed: y
-Flashrom support: y
-Release year: 2006
diff --git a/src/mainboard/asus/a8v-e_se/cmos.layout b/src/mainboard/asus/a8v-e_se/cmos.layout
deleted file mode 100644
index aae7ceb075..0000000000
--- a/src/mainboard/asus/a8v-e_se/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/a8v-e_se/devicetree.cb b/src/mainboard/asus/a8v-e_se/devicetree.cb
deleted file mode 100644
index f2d078a74e..0000000000
--- a/src/mainboard/asus/a8v-e_se/devicetree.cb
+++ /dev/null
@@ -1,97 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # APIC cluster
- chip cpu/amd/socket_939 # CPU
- device lapic 0 on end # APIC
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x1043 0 inherit
- chip northbridge/amd/amdk8 # mc0
- device pci 18.0 on # Northbridge
- # Devices on link 0, link 0 == LDT 0
- chip southbridge/via/vt8237r # Southbridge
- register "ide0_enable" = "1" # Enable IDE channel 0
- register "ide1_enable" = "1" # Enable IDE channel 1
- register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
- register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
- register "fn_ctrl_lo" = "0" # Enable SB functions
- register "fn_ctrl_hi" = "0xad" # Enable SB functions
- device pci 0.0 on end # HT
- device pci f.1 on end # IDE
- device pci 11.0 on # LPC
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- chip superio/winbond/w83627ehg # Super I/O
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2 (N/A on this board)
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 off # PS/2 keyboard & mouse (off)
- end
- device pnp 2e.106 off # Serial flash interface (SFI)
- io 0x60 = 0x100
- end
- device pnp 2e.007 off # GPIO 1
- end
- device pnp 2e.107 on # Game port
- io 0x60 = 0x201
- end
- device pnp 2e.207 on # MIDI
- io 0x62 = 0x330
- irq 0x70 = 0xa
- end
- device pnp 2e.307 off # GPIO 6
- end
- device pnp 2e.8 off # WDTO#, PLED
- end
- device pnp 2e.009 on # GPIO 2
- end
- device pnp 2e.109 off # GPIO 3
- end
- device pnp 2e.209 off # GPIO 4
- end
- device pnp 2e.309 on # GPIO 5
- end
- device pnp 2e.a off # ACPI
- end
- device pnp 2e.b on # Hardware monitor
- io 0x60 = 0x290
- irq 0x70 = 0
- end
- end
- end
- device pci 12.0 off end # VIA LAN (off, other chip used)
- end
- chip southbridge/via/k8t890 # "Southbridge" K8T890
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/asus/a8v-e_se/dsdt.asl b/src/mainboard/asus/a8v-e_se/dsdt.asl
deleted file mode 100644
index 1da24173e3..0000000000
--- a/src/mainboard/asus/a8v-e_se/dsdt.asl
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1)
-{
- #include "northbridge/amd/amdk8/util.asl"
-
- #include <southbridge/via/k8t890/acpi/sleepstates.asl>
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */
- Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },
- Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */
- Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },
- Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */
- Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
- Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */
- Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
- Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
- Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
- Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
- Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x15 },
- Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 }, /* AC97, MC97 */
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */
- })
-
- Device (PEGG)
- {
- Name (_ADR, 0x00020000)
- Name (_UID, 0x00)
- Name (_BBN, 0x02)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
- })
- }
-
- Device (PEX0)
- {
- Name (_ADR, 0x00030000)
- Name (_UID, 0x00)
- Name (_BBN, 0x03)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
- })
- }
-
- Device (PEX1)
- {
- Name (_ADR, 0x00030001)
- Name (_UID, 0x00)
- Name (_BBN, 0x04)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
- })
- }
-
- Device (PEX2)
- {
- Name (_ADR, 0x00030002)
- Name (_UID, 0x00)
- Name (_BBN, 0x05)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
- })
- }
-
- Device (PEX3)
- {
- Name (_ADR, 0x00030003)
- Name (_UID, 0x00)
- Name (_BBN, 0x06)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x28 }, /* PCIE IRQ40-IRQ43 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x29 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x2A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x2B },
- })
- }
-
- Device (ISA) {
- Name (_ADR, 0x00110000)
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () {
- IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
- IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
- }
- /* Dummy device to hold auto generated reserved resources */
- Device(MBRS) {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
- External(_CRS) /* Resource Template in SSDT */
- }
-
- }
- }
-}
diff --git a/src/mainboard/asus/a8v-e_se/mptable.c b/src/mainboard/asus/a8v-e_se/mptable.c
deleted file mode 100644
index f3d3d06207..0000000000
--- a/src/mainboard/asus/a8v-e_se/mptable.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <stdint.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
- smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
-
- mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums. */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
deleted file mode 100644
index 2df2a48815..0000000000
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2006 MSI
- * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-unsigned int get_sbdn(unsigned bus);
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <halt.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/early_ht.c"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627ehg/w83627ehg.h>
-#include <southbridge/via/vt8237r/vt8237r.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <spd.h>
-#include <northbridge/amd/amdk8/pre_f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V)
-#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <reset.h>
-void do_soft_reset(void)
-{
- uint8_t tmp;
-
- set_bios_reset();
- printk(BIOS_DEBUG, "soft reset\n");
-
- /* PCI reset */
- tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
- tmp |= 0x01;
- pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
-
- halt();
-}
-
-#include "southbridge/via/k8t890/early_car.c"
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
- return (dev >> 15) & 0x1f;
-}
-
-static void sio_init(void)
-{
- u8 reg;
-
- pnp_enter_conf_state(SERIAL_DEV);
- /* We have 24MHz input. */
- reg = pnp_read_config(SERIAL_DEV, 0x24);
- pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
- /* We have GPIO for KB/MS pin. */
- reg = pnp_read_config(SERIAL_DEV, 0x2a);
- pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
- /* We have all RESTOUT and even some reserved bits, too. */
- reg = pnp_read_config(SERIAL_DEV, 0x2c);
- pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
- pnp_exit_conf_state(SERIAL_DEV);
-
- pnp_enter_conf_state(ACPI_DEV);
- pnp_set_logical_device(ACPI_DEV);
- /*
- * Set the delay rising time from PWROK_LP to PWROK_ST to
- * 300 - 600ms, and 0 to vice versa.
- */
- reg = pnp_read_config(ACPI_DEV, 0xe6);
- pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
- /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
- reg = pnp_read_config(ACPI_DEV, 0xe4);
- pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
- pnp_exit_conf_state(ACPI_DEV);
-
- pnp_enter_conf_state(GPIO_DEV);
- pnp_set_logical_device(GPIO_DEV);
- /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
- pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */
- pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */
- pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */
- pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0 = output 1 = input */
- pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */
- pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */
- pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */
- pnp_exit_conf_state(GPIO_DEV);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- 0, 0, 0, 0,
- // Node 1
- DIMM1, DIMM3, 0, 0,
- 0, 0, 0, 0,
- };
- unsigned bsp_apicid = 0;
- int needs_reset = 0;
- struct sys_info *sysinfo = &sysinfo_car;
-
- sio_init();
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- enable_rom_decode();
-
- printk(BIOS_INFO, "now booting... fallback\n");
-
- /* Is this a CPU only reset? Or is this a secondary CPU? */
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0. */
- /* Allow the HT devices to be found. */
- enumerate_ht_chain();
- }
-
- printk(BIOS_INFO, "now booting... real_main\n");
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- /* Halt if there was a built in self test failure. */
- report_bist_failure(bist);
-
- setup_default_resource_map();
- setup_coherent_ht_domain();
- wait_all_core0_started();
-
- printk(BIOS_INFO, "now booting... Core0 started\n");
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched. */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
- init_timer();
- ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- needs_reset |= k8t890_early_setup_ht();
-
- if (needs_reset) {
- printk(BIOS_DEBUG, "ht reset -\n");
- soft_reset();
- }
-
- /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
- enable_fid_change();
- init_fidvid_bsp(bsp_apicid);
-
- /* Stop the APs so we can start them later in init. */
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl now. */
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
diff --git a/src/mainboard/asus/k8v-x/Kconfig b/src/mainboard/asus/k8v-x/Kconfig
deleted file mode 100644
index 674059b0a5..0000000000
--- a/src/mainboard/asus/k8v-x/Kconfig
+++ /dev/null
@@ -1,69 +0,0 @@
-if BOARD_ASUS_K8V_X
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_754
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_VIA_VT8237R
- select SOUTHBRIDGE_VIA_K8T890
- select SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
- select SUPERIO_WINBOND_W83697HF
- select HAVE_OPTION_TABLE
- select HAVE_PIRQ_TABLE
- select HAVE_ACPI_TABLES
- select HAVE_MP_TABLE
- select BOARD_ROMSIZE_KB_512
- select RAMINIT_SYSINFO
- select SET_FIDVID
- select K8_FORCE_2T_DRAM_TIMING
- select PIRQ_ROUTE
-
-config MAINBOARD_DIR
- string
- default asus/k8v-x
-
-config DCACHE_RAM_BASE
- hex
- default 0xcc000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x4000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MAINBOARD_PART_NUMBER
- string
- default "K8V-X"
-
-config AGP_APERTURE_SIZE
- hex
- default 0x10000000
-
-config HW_MEM_HOLE_SIZEK
- hex
- default 0x0
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config IRQ_SLOT_COUNT
- int
- default 11
-
-endif # BOARD_ASUS_K8V_X
diff --git a/src/mainboard/asus/k8v-x/Kconfig.name b/src/mainboard/asus/k8v-x/Kconfig.name
deleted file mode 100644
index 20a46315fa..0000000000
--- a/src/mainboard/asus/k8v-x/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_K8V_X
- bool "K8V-X"
diff --git a/src/mainboard/asus/k8v-x/acpi_tables.c b/src/mainboard/asus/k8v-x/acpi_tables.c
deleted file mode 100644
index b992d1ad08..0000000000
--- a/src/mainboard/asus/k8v-x/acpi_tables.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Written by Stefan Reinauer <stepan@openbios.org>.
- * ACPI FADT, FACS, and DSDT table support added by
- *
- * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
- * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/device.h>
-#include <device/pci_ids.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8x8xx.h"
-#include "northbridge/amd/amdk8/acpi.h"
-#include <cpu/amd/powernow.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-void get_bus_conf(void)
-{
- /* FIXME: implement this. */
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int gsi_base = 0x18;
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- VT8237R_APIC_ID, IO_APIC_ADDR, 0);
-
- /* Write NB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
-
- /* IRQ9 ACPI active low. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* IRQ0 -> APIC IRQ2. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0x0);
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/asus/k8v-x/board_info.txt b/src/mainboard/asus/k8v-x/board_info.txt
deleted file mode 100644
index 65a26e43fd..0000000000
--- a/src/mainboard/asus/k8v-x/board_info.txt
+++ /dev/null
@@ -1,2 +0,0 @@
-Category: desktop
-Release year: 2005
diff --git a/src/mainboard/asus/k8v-x/cmos.layout b/src/mainboard/asus/k8v-x/cmos.layout
deleted file mode 100644
index aae7ceb075..0000000000
--- a/src/mainboard/asus/k8v-x/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb
deleted file mode 100644
index 7764413c52..0000000000
--- a/src/mainboard/asus/k8v-x/devicetree.cb
+++ /dev/null
@@ -1,113 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # APIC cluster
- chip cpu/amd/socket_754 # CPU
- device lapic 0 on end # APIC
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x1043 0x80ed inherit
- chip northbridge/amd/amdk8 # mc0
- device pci 18.0 on # Northbridge
- # Devices on link 0, link 0 == LDT 0
- chip southbridge/via/vt8237r # Southbridge
- register "ide0_enable" = "1" # Enable IDE channel 0
- register "ide1_enable" = "1" # Enable IDE channel 1
- register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
- register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
- register "fn_ctrl_lo" = "0" # Enable SB functions
- register "fn_ctrl_hi" = "0xad" # Enable SB functions
- register "usb2_termination_set" = "1"
- register "usb2_termination_a" = "8"
- register "usb2_termination_b" = "8"
- register "usb2_termination_c" = "6"
- register "usb2_termination_d" = "6"
- register "usb2_termination_e" = "6"
- register "usb2_termination_f" = "6"
- register "usb2_termination_g" = "6"
- register "usb2_termination_h" = "6"
- register "usb2_dpll_set" = "1"
- register "usb2_dpll_delay" = "3"
- register "int_efgh_as_gpio" = "1"
- register "enable_gpo3" = "1"
- register "disable_gpo26_gpo27" = "1"
- register "enable_aol_2_smb_slave" = "1"
- register "enable_gpo5" = "1"
- register "gpio15_12_dir_output" = "1"
- device pci 0.0 on # HT
- subsystemid 0x1043 0x80a3
- end
- device pci a.0 on # GbE
- subsystemid 0x1043 0x811a
- end
- device pci f.0 on end # SATA
- device pci f.1 on end # IDE
- device pci 10.0 on end # USB1
- device pci 10.1 on end # USB1
- device pci 10.2 on end # USB1
- device pci 10.3 on end # USB1
- device pci 10.4 on end # USB2
- device pci 11.0 on # LPC
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip superio/winbond/w83697hf # Super I/O
- register "hwmon_fan1_divisor" = "128"
- register "hwmon_fan2_divisor" = "4"
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2 (N/A on this board)
- end
- device pnp 2e.6 off # CIR
- end
- device pnp 2e.7 off # Game port/GPIO 1
- end
- device pnp 2e.8 off # MIDI/GPIO 5
- end
- device pnp 2e.009 off # GPIO 2
- end
- device pnp 2e.109 off # GPIO 3
- end
- device pnp 2e.209 off # GPIO 4
- end
- device pnp 2e.a off # ACPI
- end
- device pnp 2e.b on # Hardware monitor
- io 0x60 = 0x290
- irq 0x70 = 0
- irq 0x24 = 0x28 # Global CR24 change bit3: MEMW# Enable
- end
- end
- end
- device pci 11.5 on # AC97 Audio
- subsystemid 0x1043 0x80b0
- end
- device pci 11.6 on end # AC97 Modem
- device pci 12.0 off end # VIA LAN (off, other chip used)
- end
- chip southbridge/via/k8t890 # "Southbridge" K8T890
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/asus/k8v-x/dsdt.asl b/src/mainboard/asus/k8v-x/dsdt.asl
deleted file mode 100644
index fc96e7630c..0000000000
--- a/src/mainboard/asus/k8v-x/dsdt.asl
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1)
-{
- #include "northbridge/amd/amdk8/util.asl"
-
- #include <southbridge/via/k8t890/acpi/sleepstates.asl>
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP slot, effectively */
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */
- Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x000BFFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x000BFFFF, 0x03, 0x00, 0x13 },
- Package (0x04) { 0x000CFFFF, 0x00, 0x00, 0x11 }, /* Slot 0xC */
- Package (0x04) { 0x000CFFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x000CFFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x000CFFFF, 0x03, 0x00, 0x10 },
- Package (0x04) { 0x000DFFFF, 0x00, 0x00, 0x12 }, /* Slot 0xD */
- Package (0x04) { 0x000DFFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x000DFFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x000DFFFF, 0x03, 0x00, 0x11 },
- Package (0x04) { 0x000EFFFF, 0x00, 0x00, 0x13 }, /* Slot 0xE */
- Package (0x04) { 0x000EFFFF, 0x01, 0x00, 0x10 },
- Package (0x04) { 0x000EFFFF, 0x02, 0x00, 0x11 },
- Package (0x04) { 0x000EFFFF, 0x03, 0x00, 0x12 },
- Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x10 }, /* Slot 0x9 */
- Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x13 },
- Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x11 }, /* Marvell 88E8001 ethernet */
- Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x14 }, /* 0xf SATA IRQ 20 */
- Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
- Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x15 }, /* USB routing */
- Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x15 },
- Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
- Package (0x04) { 0x0011FFFF, 0x02, 0x00, 0x16 } /* AC97, MC97 */
- })
-
- Device (ISA) {
- Name (_ADR, 0x00110000)
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () {
- IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
- IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
- }
- /* Dummy device to hold auto generated reserved resources */
- Device(MBRS) {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
- External(_CRS) /* Resource Template in SSDT */
- }
-
- }
- }
-}
diff --git a/src/mainboard/asus/k8v-x/irq_tables.c b/src/mainboard/asus/k8v-x/irq_tables.c
deleted file mode 100644
index 51b7dd1198..0000000000
--- a/src/mainboard/asus/k8v-x/irq_tables.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Urja Rannikko <urjaman@gmail.com>
- *
- * Code based on KFSN4-DRE irq_tables.c:
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint8_t link1, uint8_t link2,
- uint8_t link3, uint8_t slot, uint8_t rfu)
-{
- const uint16_t valid_irqs = 0xccb8;
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = link0 ? valid_irqs : 0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = link1 ? valid_irqs : 0;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = link2 ? valid_irqs : 0;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = link3 ? valid_irqs : 0;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- uint8_t *v, sum = 0;
- unsigned int slot_num = 0;
- int i;
-
- /* Align the table to be 16 byte aligned. */
- addr = ALIGN_UP(addr, 16);
-
- /* This table must be between 0xf0000 & 0x100000. */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *)(addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
- pirq->rtr_bus = 0;
- pirq->rtr_devfn = ((0x11) << 3) | 0;
- pirq->exclusive_irqs = 0;
- pirq->rtr_vendor = PCI_VENDOR_ID_VIA;
- pirq->rtr_device = PCI_DEVICE_ID_VIA_VT8237R_LPC;
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
-
- /* AGP Bridge. */
- write_pirq_info(pirq_info, 0, (0x01 << 3) | 0, 1, 2, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* ISA Bridge + AC97 + MC97 */
- write_pirq_info(pirq_info, 0, (0x11 << 3) | 0, 0, 0, 3, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* PATA and SATA. */
- write_pirq_info(pirq_info, 0, (0x0f << 3) | 0, 1, 2, 3, 5, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* USB (UHCI and EHCI) */
- write_pirq_info(pirq_info, 0, (0x10 << 3) | 0, 1, 2, 3, 5, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* 5 PCI Slots */
- write_pirq_info(pirq_info, 0, (0x0b << 3) | 0, 1, 2, 3, 5, 1, 0);
- pirq_info++;
- slot_num++;
-
- write_pirq_info(pirq_info, 0, (0x0c << 3) | 0, 2, 3, 5, 1, 2, 0);
- pirq_info++;
- slot_num++;
-
- write_pirq_info(pirq_info, 0, (0x0d << 3) | 0, 3, 5, 1, 2, 3, 0);
- pirq_info++;
- slot_num++;
-
- write_pirq_info(pirq_info, 0, (0x0e << 3) | 0, 5, 1, 2, 3, 4, 0);
- pirq_info++;
- slot_num++;
-
- write_pirq_info(pirq_info, 0, (0x09 << 3) | 0, 1, 2, 3, 5, 5, 0);
- pirq_info++;
- slot_num++;
-
- /* Ethernet */
- write_pirq_info(pirq_info, 0, (0x0a << 3) | 0, 2, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* AGP Slot. */
- write_pirq_info(pirq_info, 1, (0x00 << 3) | 0, 1, 2, 0, 0, 6, 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum)
- pirq->checksum = sum;
-
- printk(BIOS_INFO, "done.\n");
-
- /* Call copy for side effects: setting PCI IRQ registers. Hack? */
- return copy_pirq_routing_table(addr, pirq);
-}
diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c
deleted file mode 100644
index 9f35cd389b..0000000000
--- a/src/mainboard/asus/k8v-x/mainboard.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-
-u32 vt8237_ide_80pin_detect(struct device *dev)
-{
- struct device *lpc_dev;
- u16 acpi_io_base;
- u32 gpio_in;
- u32 res;
-
- lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC, 0);
- if (!lpc_dev)
- return 0;
-
- acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1;
- if (!acpi_io_base)
- return 0;
-
- /* select function GPIO29 for pin AB9 */
- pci_write_config8(lpc_dev, 0xe5, pci_read_config8(lpc_dev, 0xe5) | 0x08);
-
- gpio_in = inl(acpi_io_base + 0x48);
- /* bit 29 for primary port, clear if unconnected or 80-pin cable */
- res = gpio_in & (1 << 29) ? 0 : VT8237R_IDE0_80PIN_CABLE;
- /* bit 8 for secondary port, clear if unconnected or 80-pin cable */
- res |= gpio_in & (1 << 8) ? 0 : VT8237R_IDE1_80PIN_CABLE;
-
- printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary",
- res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40);
- printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary",
- res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40);
-
- return res;
-}
diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c
deleted file mode 100644
index 8525b029f1..0000000000
--- a/src/mainboard/asus/k8v-x/mptable.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <stdint.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8x8xx.h"
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, VIO_APIC_VADDR);
- smp_write_ioapic(mc, K8T890_APIC_ID, 0x20, (void *)K8T890_APIC_BASE);
-
- mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x11 << 2) | 2, VT8237R_APIC_ID, 0x16);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 0, K8T890_APIC_ID, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 1, K8T890_APIC_ID, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 2, K8T890_APIC_ID, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x6, (0x00 << 2) | 3, K8T890_APIC_ID, 0x13);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, bus_isa);
- /* There is no extension information... */
-
- /* Compute the checksums. */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
deleted file mode 100644
index 053028497a..0000000000
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2006 MSI
- * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-unsigned int get_sbdn(unsigned bus);
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <halt.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <cpu/x86/lapic.h>
-#include "northbridge/amd/amdk8/early_ht.c"
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83697hf/w83697hf.h>
-#include <southbridge/via/vt8237r/vt8237r.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <spd.h>
-#include <northbridge/amd/amdk8/pre_f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <reset.h>
-void do_soft_reset(void)
-{
- uint8_t tmp;
-
- set_bios_reset();
- printk(BIOS_DEBUG, "soft reset\n");
-
- /* PCI reset */
- tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
- tmp |= 0x01;
- pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
-
- halt();
-}
-
-#include "southbridge/via/k8t890/early_car.c"
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "northbridge/amd/amdk8/raminit.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
- return (dev >> 15) & 0x1f;
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- // Node 0
- DIMM0, DIMM1, DIMM2, 0,
- 0, 0, 0, 0,
- // Node 1
- 0, 0, 0, 0,
- 0, 0, 0, 0,
- };
- unsigned bsp_apicid = 0;
- int needs_reset = 0;
- struct sys_info *sysinfo = &sysinfo_car;
-
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
- enable_rom_decode();
-
- printk(BIOS_INFO, "now booting... fallback\n");
-
- /* Is this a CPU only reset? Or is this a secondary CPU? */
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0. */
- /* Allow the HT devices to be found. */
- enumerate_ht_chain();
- }
-
- printk(BIOS_INFO, "now booting... real_main\n");
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- /* Halt if there was a built in self test failure. */
- report_bist_failure(bist);
-
- setup_default_resource_map();
- setup_coherent_ht_domain();
- wait_all_core0_started();
-
- printk(BIOS_INFO, "now booting... Core0 started\n");
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched. */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
- init_timer();
- ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- needs_reset |= k8t890_early_setup_ht();
-
- if (needs_reset) {
- printk(BIOS_DEBUG, "ht reset -\n");
- soft_reset();
- }
-
- /* the HT settings needs to be OK, because link freq change may cause HT disconnect */
- vt8237_sb_enable_fid_vid();
- enable_fid_change();
- init_fidvid_bsp(bsp_apicid);
-
- /* Stop the APs so we can start them later in init. */
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl now. */
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
-
- /* this seems to be some GPIO on the SMBus--in any case, setting these
- * two bits reduces the pullup impedance of the bus lines and is required
- * in order to be able to read SPD info */
- smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80);
- smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10);
-
- unsigned char mask;
-
- mask = 0;
-// mask |= 1 /* AGP voltage 1.7 V (not verified, just vendor BIOS value) */
-// mask |= 2 /* V-Link voltage 2.6 V (not verified either) */
- smbus_write_byte(0x4a, 0x00, (smbus_read_byte(0x4a, 0x00) & ~0x0f) | (0x0f ^ (mask << 2)));
- smbus_write_byte(0x4a, 0x01, (smbus_read_byte(0x4a, 0x01) & ~0x03) | (0x03 ^ mask));
-
- mask = 25; /* RAM voltage in decivolts, valid range from 25 to 28 */
- mask = 3 - (mask - 25);
- smbus_write_byte(0x4a, 0x02, 0x4f | (mask << 4));
- smbus_write_byte(0x4a, 0x03, 0x04 | mask);
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
diff --git a/src/mainboard/asus/kfsn4-dre_k8/Kconfig b/src/mainboard/asus/kfsn4-dre_k8/Kconfig
deleted file mode 100644
index 0d13a4ece4..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/Kconfig
+++ /dev/null
@@ -1,98 +0,0 @@
-if BOARD_ASUS_KFSN4_DRE_K8
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_F
- select DIMM_DDR2
- select DIMM_REGISTERED
- select QRANK_DIMM_SUPPORT
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_CK804
- select SUPERIO_WINBOND_W83627THG
- select PARALLEL_CPU_INIT
- select HAVE_HARD_RESET
- select HAVE_OPTION_TABLE
- select HAVE_CMOS_DEFAULT
- select HAVE_PIRQ_TABLE
- select HAVE_MP_TABLE
- select HAVE_ACPI_TABLES
- select LIFT_BSP_APIC_ID
- select BOARD_ROMSIZE_KB_1024
- select ENABLE_APIC_EXT_ID
- select K8_ALLOCATE_IO_RANGE
- select DRIVERS_I2C_W83793
- select DRIVERS_XGI_Z9S
-
-config MAINBOARD_DIR
- string
- default "asus/kfsn4-dre_k8"
-
-config BOOTBLOCK_MAINBOARD_INIT
- string
- default "mainboard/asus/kfsn4-dre_k8/bootblock.c"
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x08000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MAINBOARD_PART_NUMBER
- string
- default "KFSN4-DRE_K8"
-
-config HW_MEM_HOLE_SIZEK
- hex
- default 0x100000
-
-config MAX_CPUS
- int
- default 4
-
-config MAX_PHYSICAL_CPUS
- int
- default 2
-
-config MEM_TRAIN_SEQ
- int
- default 1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config IRQ_SLOT_COUNT
- int
- default 13
-
-config CK804_PCI_E_X
- int
- default 1
-
-config CK804_PCIE_PME_WAKE
- bool
- default y
-
-config ONBOARD_VGA_IS_PRIMARY
- bool
- default y
-
-config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
- bool
- default y
-
-config MAX_REBOOT_CNT
- int
- default 10
-
-endif # BOARD_ASUS_KFSN4_DRE_K8
diff --git a/src/mainboard/asus/kfsn4-dre_k8/Kconfig.name b/src/mainboard/asus/kfsn4-dre_k8/Kconfig.name
deleted file mode 100644
index 5720f3ef3f..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_KFSN4_DRE_K8
- bool "KFSN4-DRE_K8"
diff --git a/src/mainboard/asus/kfsn4-dre_k8/acpi/pm_ctrl.asl b/src/mainboard/asus/kfsn4-dre_k8/acpi/pm_ctrl.asl
deleted file mode 100644
index 0afb841435..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/acpi/pm_ctrl.asl
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- * Copyright (C) 2010 - 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * WARNING: Sleep/Wake is a work in progress and is still somewhat flaky!
- */
-
- /* SuperIO control port */
- Name (SPIO, 0x2E)
-
- /* SuperIO control map */
- OperationRegion (SPIM, SystemIO, SPIO, 0x02)
- Field (SPIM, ByteAcc, NoLock, Preserve) {
- INDX, 8,
- DATA, 8
- }
-
- /* SuperIO control registers */
- IndexField (INDX, DATA, ByteAcc, NoLock, Preserve) {
- Offset (0x07),
- CR07, 8, /* Logical device number */
- Offset (0x2C),
- CR2C, 8, /* GPIO3 multiplexed pin selection */
- Offset (0x30),
- CR30, 8, /* Logical device activation control register */
- Offset (0xE0),
- CRE0, 8, /* Wake control register */
- Offset (0xE6),
- CRE6, 8, /* Mouse wake event configuration register */
- Offset (0xF1),
- CRF1, 8, /* GPIO3 data register */
- Offset (0xF3),
- CRF3, 8, /* SUSLED mode register */
- Offset (0xF6),
- CRF6, 8, /* SMI/PME event generation control register */
- Offset (0xF9),
- CRF9, 8, /* ACPI PME configuration register */
- }
-
- /* Southbridge control ports */
- /* Both are offsets from PM base address (0x2000) */
- Name (SBC1, 0x2090) /* Offset 0x90 */
- Name (SBC2, 0x2400) /* Offset 0x400 */
-
- /* Southbridge control maps */
- OperationRegion (SBM1, SystemIO, SBC1, 0x10)
- Field (SBM1, ByteAcc, NoLock, Preserve) {
- S1CT, 2,
- Offset (0x04),
- S3CT, 2,
- Offset (0x08),
- S4CT, 2,
- Offset (0x0C),
- S5CT, 2,
- }
- OperationRegion (SBM2, SystemIO, SBC2, 0x08)
- Field (SBM2, ByteAcc, NoLock, Preserve) {
- , 15,
- PS1S, 1,
- , 31,
- PS1E, 1,
- }
-
- /* Wake status package */
- Name(WKST,Package(){Zero, Zero})
-
- /*
- * \_WAK System Wake method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2
- *
- * Exit:
- * Return package of 2 DWords
- * Dword 1 - Status
- * 0x00000000 wake succeeded
- * 0x00000001 Wake was signaled but failed due to lack of power
- * 0x00000002 Wake was signaled but failed due to thermal condition
- * Dword 2 - Power Supply state
- * if non-zero the effective S-state the power supply entered
- */
- Method(\_WAK, 1) {
- /* Set up LEDs */
- /* Access SuperIO GPIO3/GPIO4 device */
- Store(0x87, INDX)
- Store(0x87, INDX)
- Store(0x09, CR07)
-
- /* Set GPIO3 pin 64 (power LED) to GP37 mode */
- And(CR2C, 0xF3, Local0)
- Or(Local0, 0x04, CR2C)
-
- /* Set power LED to steady on */
- Or(CRF1, 0x80, CRF1)
-
- /* Restore default SuperIO access */
- Store(0xAA, INDX)
-
- /* Configure SuperIO for wake */
- /* Access SuperIO ACPI device */
- Store(0x87, INDX)
- Store(0x87, INDX)
- Store(0x0A, CR07)
-
- if (LEqual(Arg0, One)) /* Resuming from power state S1 */
- {
- /* Set power management to SMI mode and disable SMI events */
- And(CRF9, 0xFA, CRF9)
-
- /* Deactivate the ACPI device */
- Store(Zero, CR30)
-
- /* Disable PS/2 SMI/PME events */
- And(CRF6, 0xCF, CRF6)
- }
- if (Lor(LEqual(Arg0, 0x03), LEqual(Arg0, 0x04))) /* Resuming from power state S3 or S4 */
- {
- /* Disable PS/2 wake */
- And(CRE0, 0x1D, CRE0)
- And(CRE6, 0x7F, CRE6)
- }
-
- /* Restore default SuperIO access */
- Store(0xAA, INDX)
-
- /* Configure southbridge for wake */
- Store(Zero, PS1E)
- Store(0x02, S1CT)
- Store(0x02, S3CT)
- Store(0x02, S4CT)
- Store(0x02, S5CT)
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-
- Return(WKST)
- } /* End Method(\_WAK) */
-
- /*
- * \_PTS - Prepare to Sleep method
- *
- * Entry:
- * Arg0=The value of the sleeping state S1=1, S2=2, etc
- *
- * Exit:
- * -none-
- *
- * The _PTS control method is executed at the beginning of the sleep process
- * for S1-S5. The sleeping value is passed to the _PTS control method. This
- * control method may be executed a relatively long time before entering the
- * sleep state and the OS may abort the operation without notification to
- * the ACPI driver. This method cannot modify the configuration or power
- * state of any device in the system.
- */
- Method(\_PTS, 1) {
- /* Set up LEDs */
- if (LEqual(Arg0, One)) /* Power state S1 requested */
- {
- /* Access SuperIO GPIO3/GPIO4 device */
- Store(0x87, INDX)
- Store(0x87, INDX)
- Store(0x09, CR07)
-
- /* Set GPIO3 pin 64 (power LED) to SUSLED mode */
- And(CR2C, 0xF3, CR2C)
-
- /* Set suspend LED to 1Hz toggle pulse with 50% duty cycle */
- Or(CRF3, 0x80, CRF3)
-
- /* Restore default SuperIO access */
- Store(0xAA, INDX)
- }
-
- /* Configure SuperIO for sleep */
- /* Access SuperIO ACPI device */
- Store(0x87, INDX)
- Store(0x87, INDX)
- Store(0x0A, CR07)
-
- /* Disable PS/2 wakeup and connect PANSW_IN to PANSW_OUT */
- And(CRE0, 0x1F, CRE0)
-
- if (LEqual(Arg0, One)) /* Power state S1 requested */
- {
- /* Set power management to PME mode and enable PME events */
- Or(CRF9, 0x05, CRF9)
-
- /* Activate the ACPI device */
- Store(One, CR30)
-
- /* Enable PS/2 keyboard SMI/PME events */
- And(CRF6, 0xEF, CRF6)
-
- /* Enable PS/2 keyboard wake */
- Or(CRE0, 0x40, CRE0)
-
- /* Enable PS/2 mouse SMI/PME events */
- And(CRF6, 0xDF, CRF6)
-
- /* Enable PS/2 mouse wake */
- Or(CRE0, 0x20, CRE0)
- }
- else {
- /* Enable PS/2 keyboard wake on any keypress */
- Or(CRE0, 0x41, CRE0)
-
- /* Enable PS/2 mouse wake on any click */
- Or(CRE0, 0x22, CRE0)
- Or(CRE6, 0x80, CRE6)
- }
-
- /* Restore default SuperIO access */
- Store(0xAA, INDX)
-
- /* Configure southbridge for sleep */
- Store(One, PS1S)
- Store(One, PS1E)
-
- /* On older chips, clear PciExpWakeDisEn */
- /*if (LLessEqual(\_SB.SBRI, 0x13)) {
- * Store(0,\_SB.PWDE)
- *}
- */
-
- /* Clear wake status structure. */
- Store(0, Index(WKST,0))
- Store(0, Index(WKST,1))
- } /* End Method(\_PTS) */
diff --git a/src/mainboard/asus/kfsn4-dre_k8/acpi_tables.c b/src/mainboard/asus/kfsn4-dre_k8/acpi_tables.c
deleted file mode 100644
index 6061f89819..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/acpi_tables.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * ACPI support
- * written by Stefan Reinauer <stepan@openbios.org>
- * (C) 2005 Stefan Reinauer
- *
- * Copyright 2005 AMD
- * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
- *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <assert.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-/* APIC */
-unsigned long acpi_fill_madt(unsigned long current)
-{
- struct device *dev;
- struct resource *res;
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write NVIDIA CK804 IOAPIC. */
- dev = dev_find_slot(0x0, PCI_DEVFN(sysconf.sbdn + 0x1, 0));
- ASSERT(dev != NULL);
-
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- ASSERT(res != NULL);
-
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current,
- CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS, res->base, 0);
-
- /* Initialize interrupt mapping if mptable.c didn't. */
- if (!IS_ENABLED(CONFIG_GENERATE_MP_TABLE)) {
- /* Copied from mptable.c */
- /* Enable interrupts for commonly used devices (USB, SATA, etc.) */
- pci_write_config32(dev, 0x7c, 0x0d800018);
- pci_write_config32(dev, 0x80, 0xd8002009);
- pci_write_config32(dev, 0x84, 0x00000001);
- }
-
-// /* IRQ of timer (override IRQ0 --> APIC IRQ2) */
-// current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-// current, 0, 0, 2, 0);
- /* IRQ9 */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
- /* IRQ14 */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 14, 14, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH);
- /* IRQ15 */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 15, 15, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH);
-
- /* create all subtables for processors */
- /* acpi_create_madt_lapic_nmis returns current, not size. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/asus/kfsn4-dre_k8/board_info.txt b/src/mainboard/asus/kfsn4-dre_k8/board_info.txt
deleted file mode 100644
index 678373ad2c..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Category: server
-ROM package: PLCC-32
-ROM protocol: LPC
-ROM socketed: y
-Flashrom support: y
-Release year: 2007
diff --git a/src/mainboard/asus/kfsn4-dre_k8/bootblock.c b/src/mainboard/asus/kfsn4-dre_k8/bootblock.c
deleted file mode 100644
index 454443f370..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/bootblock.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <pc80/mc146818rtc.h>
-
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627thg/w83627thg.h>
-
-#define GPIO_DEV PNP_DEV(0x2e, W83627THG_GPIO3)
-
-#define WINBOND_ENTRY_KEY 0x87
-#define WINBOND_EXIT_KEY 0xAA
-
-/* Enable configuration: pass entry key '0x87' into index port dev. */
-static void pnp_enter_conf_state(pnp_devfn_t dev)
-{
- u16 port = dev >> 8;
- outb(WINBOND_ENTRY_KEY, port);
- outb(WINBOND_ENTRY_KEY, port);
-}
-
-/* Disable configuration: pass exit key '0xAA' into index port dev. */
-static void pnp_exit_conf_state(pnp_devfn_t dev)
-{
- u16 port = dev >> 8;
- outb(WINBOND_EXIT_KEY, port);
-}
-
-uint8_t bootblock_read_recovery_jumper(pnp_devfn_t dev)
-{
- uint8_t recovery_enabled = 0;
-
- pnp_enter_conf_state(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 1); /* Enable GPIO3 */
- pnp_write_config(dev, 0xf0, 0xff); /* Set GPIO3 to input */
- recovery_enabled = !(pnp_read_config(dev, 0xf1) & 0x08); /* Read GP33 */
- pnp_exit_conf_state(dev);
-
- return recovery_enabled;
-}
-
-void bootblock_mainboard_init(void)
-{
- uint8_t recovery_enabled;
- unsigned char addr;
- unsigned char byte;
-
- recovery_enabled = bootblock_read_recovery_jumper(GPIO_DEV);
- if (recovery_enabled) {
-#if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
- /* Clear NVRAM checksum */
- for (addr = LB_CKS_RANGE_START; addr <= LB_CKS_RANGE_END; addr++) {
- cmos_write(0x0, addr);
- }
-
- /* Set fallback boot */
- byte = cmos_read(RTC_BOOT_BYTE);
- byte &= 0xfc;
- cmos_write(byte, RTC_BOOT_BYTE);
-#else
- /* FIXME
- * Figure out how to recover if the option table is not available
- */
-#endif
- }
-}
diff --git a/src/mainboard/asus/kfsn4-dre_k8/cmos.default b/src/mainboard/asus/kfsn4-dre_k8/cmos.default
deleted file mode 100644
index d3a8081d95..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/cmos.default
+++ /dev/null
@@ -1,12 +0,0 @@
-debug_level = Spew
-multi_core = Enable
-slow_cpu = off
-hypertransport_speed_limit = Auto
-max_mem_clock = DDR2-800
-ECC_memory = Enable
-hw_scrubber = Enable
-interleave_chip_selects = Enable
-interleave_nodes = Disable
-interleave_memory_channels = Enable
-power_on_after_fail = Enable
-boot_option = Fallback
diff --git a/src/mainboard/asus/kfsn4-dre_k8/cmos.layout b/src/mainboard/asus/kfsn4-dre_k8/cmos.layout
deleted file mode 100644
index 86b95a94e4..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/cmos.layout
+++ /dev/null
@@ -1,117 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-393 3 r 0 unused
-396 1 e 1 hw_scrubber
-397 1 e 1 interleave_chip_selects
-398 1 e 1 interleave_nodes
-399 1 e 1 interleave_memory_channels
-408 2 e 8 max_mem_clock
-410 1 e 2 multi_core
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-446 1 e 1 power_on_after_fail
-456 1 e 1 ECC_memory
-458 4 e 11 hypertransport_speed_limit
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 0 Emergency
-6 1 Alert
-6 2 Critical
-6 3 Error
-6 4 Warning
-6 5 Notice
-6 6 Information
-6 7 Debug
-6 8 Spew
-8 0 DDR2-800
-8 1 DDR2-667
-8 2 DDR2-533
-8 3 DDR2-400
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-10 0 Disabled
-10 1 40ns
-10 2 80ns
-10 3 160ns
-10 4 320ns
-10 5 640ns
-10 6 1.28us
-10 7 2.56us
-10 8 5.12us
-10 9 10.2us
-10 10 20.5us
-10 11 41us
-10 12 81.9us
-10 13 163.8us
-10 14 327.7us
-10 15 655.4us
-10 16 1.31ms
-10 17 2.62ms
-10 18 5.24ms
-10 19 10.49ms
-10 20 20.97ms
-10 21 42ms
-10 22 84ms
-11 0 Auto
-11 1 2.6GHz
-11 2 2.4GHz
-11 3 2.2GHz
-11 4 2.0GHz
-11 5 1.8GHz
-11 6 1.6GHz
-11 7 1.4GHz
-11 8 1.2GHz
-11 9 1.0GHz
-11 10 800MHz
-11 11 600MHz
-11 12 500MHz
-11 13 400MHz
-11 14 300MHz
-11 15 200MHz
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb b/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb
deleted file mode 100644
index a02b234d04..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb
+++ /dev/null
@@ -1,197 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_F # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x1043 0x8162 inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- register "maximum_memory_capacity" = "0x1000000000" # 64GB
- device pci 18.0 on end # Link 0 == LDT 0
- device pci 18.0 on # Link 1 == LDT 1 [SB on link 1]
- chip southbridge/nvidia/ck804 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/winbond/w83627thg # Super I/O
- device pnp 2e.0 on # Floppy
- # Set up interface resources
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off end # Parallel port
- device pnp 2e.2 on # Com1
- # Set up interface resources
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 on # Com2
- # Set up interface resources
- io 0x60 = 0x2f8
- irq 0x70 = 3
- # Select correct package I/O pins
- io 0xf1 = 0x04
- end
- device pnp 2e.5 on # PS/2 keyboard & mouse
- # Set up interface resources
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.7 off end # Game port, MIDI, GPIO 1 & 5
- device pnp 2e.8 off end # GPIO 2
- device pnp 2e.9 on end # GPIO 3, GPIO 4
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # Hardware monitor
- # Set up interface resources
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
- end
- device pci 1.1 on # SM 0
- chip drivers/generic/generic # DIMM n-0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM n-0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM n-0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM n-0-1-1
- device i2c 53 on end
- end
- chip drivers/generic/generic # DIMM n-1-0-0
- device i2c 54 on end
- end
- chip drivers/generic/generic # DIMM n-1-0-1
- device i2c 55 on end
- end
- chip drivers/generic/generic # DIMM n-1-1-0
- device i2c 56 on end
- end
- chip drivers/generic/generic # DIMM n-1-1-1
- device i2c 57 on end
- end
- chip drivers/i2c/w83793
- register "mfc" = "0x29" # Enable FANIN1/FANIN12, FANIN9/FANIN10, and FANIN8/FANCTRL8 inputs
- register "fanin" = "0x7f" # Enable monitoring of FANIN6 - FANIN12
- register "fanin_sel" = "0x0f" # Connect FANIN9 - FANIN12 to pins 37 - 40
- register "peci_agent_conf" = "0x33" # Set Intel CPU PECI agent domain (not used by AMD but may affect chip operation)
- register "tcase0" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation)
- register "tcase1" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation)
- register "tcase2" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation)
- register "tcase3" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation)
- register "tr_enable" = "0x03" # Enable montoring of TR1 and TR2
- register "td_mode_select" = "0x05" # Use internal temperature sensors and disable unconnected TD3/TD4
- register "td1_critical_temperature" = "85" # Set TD1 (CPU0) critical temperature to 85°C
- register "td1_critical_hysteresis" = "80" # Set TD1 (CPU0) critical hysteresis temperature to 80°C
- register "td1_warning_temperature" = "70" # Set TD1 (CPU0) warning temperature to 70°C
- register "td1_warning_hysteresis" = "65" # Set TD1 (CPU0) warning hysteresis temperature to 65°C
- register "td2_critical_temperature" = "85" # Set TD2 (CPU1) critical temperature to 85°C
- register "td2_critical_hysteresis" = "80" # Set TD2 (CPU1) critical hysteresis temperature to 80°C
- register "td2_warning_temperature" = "70" # Set TD2 (CPU1) warning temperature to 70°C
- register "td2_warning_hysteresis" = "65" # Set TD2 (CPU1) warning hysteresis temperature to 65°C
- register "tr1_critical_temperature" = "60" # Set TR1 (mainboard) critical temperature to 60°C
- register "tr1_critical_hysteresis" = "55" # Set TR1 (mainboard) critical hysteresis temperature to 55°C
- register "tr1_warning_temperature" = "50" # Set TR1 (mainboard) warning temperature to 50°C
- register "tr1_warning_hysteresis" = "45" # Set TR1 (mainboard) warning hysteresis temperature to 45°C
- register "critical_temperature" = "80" # Set critical temperature to 80°C
- register "fanctrl1" = "0x48" # Set Fan 4 and Fan 7 to output buffer mode, all others to open drain
- register "fanctrl2" = "0x01" # Set Fan 4 to Fan 7 to output buffer mode, Fan 1 to DC mode
- register "first_valid_fan_number" = "2" # Fan 1/Fan 2 controls and sensors are not connected to anything
- register "td1_fan_select" = "0x00" # All fans to manual mode (no dependence on TD1)
- register "td2_fan_select" = "0x00" # All fans to manual mode (no dependence on TD2)
- register "td3_fan_select" = "0x00" # All fans to manual mode (no dependence on TD3)
- register "td4_fan_select" = "0x00" # All fans to manual mode (no dependence on TD4)
- register "tr1_fan_select" = "0x00" # All fans to manual mode (no dependence on TR1)
- register "tr2_fan_select" = "0x00" # All fans to manual mode (no dependence on TR2)
- register "fan1_nonstop" = "7" # Set Fan 1 minimum speed
- register "fan2_nonstop" = "7" # Set Fan 2 minimum speed
- register "fan3_nonstop" = "7" # Set Fan 3 minimum speed
- register "fan4_nonstop" = "7" # Set Fan 4 minimum speed
- register "fan5_nonstop" = "7" # Set Fan 5 minimum speed
- register "fan6_nonstop" = "7" # Set Fan 6 minimum speed
- register "fan7_nonstop" = "7" # Set Fan 7 minimum speed
- register "fan8_nonstop" = "7" # Set Fan 8 minimum speed
- register "default_speed" = "100" # All fans to full speed on power up
- register "fan1_duty" = "100" # Fan 1 to full speed
- register "fan2_duty" = "100" # Fan 2 to full speed
- register "fan3_duty" = "100" # Fan 3 to full speed
- register "fan4_duty" = "100" # Fan 4 to full speed
- register "fan5_duty" = "100" # Fan 5 to full speed
- register "fan6_duty" = "100" # Fan 6 to full speed
- register "fan7_duty" = "100" # Fan 7 to full speed
- register "fan8_duty" = "100" # Fan 8 to full speed
- register "vcorea_high_limit_mv" = "1500" # VCOREA (Node 0) high limit to 1.5V
- register "vcorea_low_limit_mv" = "900" # VCOREA (Node 0) low limit to 0.9V
- register "vcoreb_high_limit_mv" = "1500" # VCOREB (Node 1) high limit to 1.5V
- register "vcoreb_low_limit_mv" = "900" # VCOREB (Node 1) low limit to 0.9V
- register "vtt_high_limit_mv" = "1250" # VTT (HT link voltage) high limit to 1.25V
- register "vtt_low_limit_mv" = "1150" # VTT (HT link voltage) low limit to 1.15V
- register "vsen1_high_limit_mv" = "1900" # VSEN1 (Node 0 RAM voltage) high limit to 1.9V
- register "vsen1_low_limit_mv" = "1700" # VSEN1 (Node 0 RAM voltage) low limit to 1.7V
- register "vsen2_high_limit_mv" = "1900" # VSEN2 (Node 1 RAM voltage) high limit to 1.9V
- register "vsen2_low_limit_mv" = "1700" # VSEN2 (Node 1 RAM voltage) low limit to 1.7V
- register "vsen3_high_limit_mv" = "3500" # VSEN3 (+3.3V) high limit to 3.5V
- register "vsen3_low_limit_mv" = "3100" # VSEN3 (+3.3V) low limit to 3.1V
- register "vsen4_high_limit_mv" = "1070" # VSEN4 (+12V, scaling factor ~12.15) high limit to 13V
- register "vsen4_low_limit_mv" = "905" # VSEN4 (+12V, scaling factor ~12.15) low limit to 11V
- register "vdd_high_limit_mv" = "5200" # 5VDD high limit to 5.2V
- register "vdd_low_limit_mv" = "4800" # 5VDD low limit to 4.8V
- register "vsb_high_limit_mv" = "5200" # 5VSB high limit to 5.2V
- register "vsb_low_limit_mv" = "4800" # 5VSB low limit to 4.8V
- register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V
- register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V
- device i2c 0x2f on end
- end
- end
- device pci 1.1 on end # SM 1
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 off end # AC'97 Audio (N/A)
- device pci 4.1 off end # AC'97 Modem (N/A)
- device pci 6.0 on end # IDE
- device pci 7.0 on end # SATA 0
- device pci 8.0 on end # SATA 1
- device pci 9.0 on # Bridge
- device pci 4.0 on end # VGA
- end
- device pci a.0 off end
- device pci b.0 on # Bridge
- device pci 0.0 on end # NIC A
- end
- device pci c.0 on # Bridge
- device pci 0.0 on end # LSI SAS
- end
- device pci d.0 on # Bridge
- device pci 0.0 on end # NIC B
- end
- device pci e.0 on # Bridge
- # Slot # PCI E 0
- end
- device pci f.0 off end
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- end
- end
- device pci 18.0 on end # Link 2 == LDT 2
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- device pci 18.4 on end
- device pci 19.0 on end # Link 0 == LDT 0
- device pci 19.0 on end # Link 1 == LDT 1
- device pci 19.0 on end # Link 2 == LDT 2
- device pci 19.1 on end
- device pci 19.2 on end
- device pci 19.3 on end
- device pci 19.4 on end
- end
- end
-end
diff --git a/src/mainboard/asus/kfsn4-dre_k8/dsdt.asl b/src/mainboard/asus/kfsn4-dre_k8/dsdt.asl
deleted file mode 100644
index ce01a49db8..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/dsdt.asl
+++ /dev/null
@@ -1,947 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- * Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * WARNING: Sleep/Wake is a work in progress and is still somewhat flaky!
- * Everything else does to the best of my knowledge... (T.P. 01/26/2015)
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-/*
- * PCI link routing templates taken from ck804.asl and modified for this board
- */
-
-DefinitionBlock (
- "DSDT.AML", /* Output filename */
- "DSDT", /* Signature */
- 0x02, /* DSDT Revision, needs to be 2 for 64bit */
- "ASUS ", /* OEMID */
- "COREBOOT", /* TABLE ID */
- 0x00000001 /* OEM Revision */
- )
-{
- #include "northbridge/amd/amdk8/util.asl"
-
- /* Some global data */
- Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
- Name(OSV, Ones) /* Assume nothing */
- Name(PICM, One) /* Assume APIC */
-
- /* HPET control */
- Name (SHPB, 0xFED00000)
- Name (SHPL, 0x1000)
-
- /* Define power states */
- Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) /* Normal operation */
- Name (_S1, Package () { 0x01, 0x00, 0x00, 0x00 }) /* Standby */
- /* Name (_S3, Package () { 0x05, 0x00, 0x00, 0x00 }) */ /* Not supported by hardware */
- /* Name (_S4, Package () { 0x06, 0x00, 0x00, 0x00 }) */
- Name (\_S5, Package () { 0x07, 0x00, 0x00, 0x00 }) /* Hard power off */
-
- /* The _PIC method is called by the OS to choose between interrupt
- * routing via the i8259 interrupt controller or the APIC.
- *
- * _PIC is called with a parameter of 0 for i8259 configuration and
- * with a parameter of 1 for Local Apic/IOAPIC configuration.
- */
- Method (_PIC, 1, Serialized) {
- Store (Arg0, PICM)
- }
-
- /* _PR CPU0 is dynamically supplied by SSDT */
- /* CPU objects and _PSS entries are dynamically supplied by SSDT */
-
- Scope(\_GPE) { /* Start Scope GPE */
- /* VGA controller PME# */
- Method(_L00) {
- /* Level-Triggered GPE */
- Notify(\_SB.PCI0.VGAC, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* Keyboard controller PME# */
- Method(_L03) {
- /* Level-Triggered GPE */
- Notify(\_SB.PCI0.LPC.KBD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.LPC.MOU, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* USB2 PME# */
- Method(_L05) {
- /* Level-Triggered GPE */
- Notify (\_SB.PCI0.USB2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* Slot PME# */
- Method(_L0B) {
- /* Level-Triggered GPE */
- Notify (\_SB.PCI0.PCIE.SLT1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PCI0.LSIC.SLT2, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* USB0 PME# */
- Method(_L0D) {
- /* Level-Triggered GPE */
- Notify (\_SB.PCI0.USB0, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* Keyboard controller PME# */
- Method(_L10) {
- /* Level-Triggered GPE */
- Notify(\_SB.PCI0.LPC.KBD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PCI0.LPC.MOU, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- /* PCIe PME# */
- Method(_L11) {
- /* Level-Triggered GPE */
- Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PCI0.PCIE, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PCI0.LSIC, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify (\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
- }
-
- } /* End Scope GPE */
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device (CK804) */
- Device (PCI0)
- {
- /* BUS0 root bus */
-
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00180001)
- Name (_UID, 0x00)
-
- Name (HCIN, 0x00) // HC1
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- /* Operating System Capabilities Method */
- Method(_OSC,4)
- {
- /* Let OS control everything */
- Return (Arg3)
- }
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
- External (CBST)
-
- /* PCI Routing Tables */
- Name (PR00, Package () {
- /* PIC */
- /* ISA Bridge */
- Package (0x04) { 0x0001FFFF, 0x00, LKSM, 0x00 },
-
- /* USB */
- Package (0x04) { 0x0002FFFF, 0x00, LUB0, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x01, LUB2, 0x00 },
-
- /* SATA 0 */
- Package (0x04) { 0x0007FFFF, 0x00, LSA0, 0x00 },
-
- /* SATA 1 */
- Package (0x04) { 0x0008FFFF, 0x00, LSA1, 0x00 },
-
- /* NIC A (Bridge) */
- Package (0x04) { 0x000BFFFF, 0x00, LNKB, 0x00 },
- Package (0x04) { 0x000BFFFF, 0x01, LNKC, 0x00 },
- Package (0x04) { 0x000BFFFF, 0x02, LNKD, 0x00 },
- Package (0x04) { 0x000BFFFF, 0x03, LNKA, 0x00 },
-
- /* NIC B (Bridge) */
- Package (0x04) { 0x000CFFFF, 0x00, LNKA, 0x00 },
- Package (0x04) { 0x000CFFFF, 0x01, LNKB, 0x00 },
- Package (0x04) { 0x000CFFFF, 0x02, LNKC, 0x00 },
- Package (0x04) { 0x000CFFFF, 0x03, LNKD, 0x00 },
-
- /* LSI SAS Controller (Bridge) */
- Package (0x04) { 0x000DFFFF, 0x00, LNKD, 0x00 },
- Package (0x04) { 0x000DFFFF, 0x01, LNKA, 0x00 },
- Package (0x04) { 0x000DFFFF, 0x02, LNKB, 0x00 },
- Package (0x04) { 0x000DFFFF, 0x03, LNKC, 0x00 },
-
- /* PCI-E Slot (Bridge) */
- Package (0x04) { 0x000EFFFF, 0x00, LNKC, 0x00 },
- Package (0x04) { 0x000EFFFF, 0x01, LNKD, 0x00 },
- Package (0x04) { 0x000EFFFF, 0x02, LNKA, 0x00 },
- Package (0x04) { 0x000EFFFF, 0x03, LNKB, 0x00 },
- })
-
- Name (AR00, Package () {
- /* APIC */
- /* ISA Bridge */
- Package (0x04) { 0x0001FFFF, 0x00, LKSM, 0x00 },
-
- /* USB */
- Package (0x04) { 0x0002FFFF, 0x00, LUB0, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x01, LUB2, 0x00 },
-
- /* SATA 0 */
- Package (0x04) { 0x0007FFFF, 0x00, LSA0, 0x00 },
-
- /* SATA 1 */
- Package (0x04) { 0x0008FFFF, 0x00, LSA1, 0x00 },
-
- /* NIC A (Bridge) */
- Package (0x04) { 0x000BFFFF, 0x00, LNIB, 0x00 },
- Package (0x04) { 0x000BFFFF, 0x01, LNIC, 0x00 },
- Package (0x04) { 0x000BFFFF, 0x02, LNND, 0x00 },
- Package (0x04) { 0x000BFFFF, 0x03, LNIA, 0x00 },
-
- /* NIC B (Bridge) */
- Package (0x04) { 0x000CFFFF, 0x00, LNIA, 0x00 },
- Package (0x04) { 0x000CFFFF, 0x01, LNIB, 0x00 },
- Package (0x04) { 0x000CFFFF, 0x02, LNIC, 0x00 },
- Package (0x04) { 0x000CFFFF, 0x03, LNND, 0x00 },
-
- /* LSI SAS Controller (Bridge) */
- Package (0x04) { 0x000DFFFF, 0x00, LNND, 0x00 },
- Package (0x04) { 0x000DFFFF, 0x01, LNIA, 0x00 },
- Package (0x04) { 0x000DFFFF, 0x02, LNIB, 0x00 },
- Package (0x04) { 0x000DFFFF, 0x03, LNIC, 0x00 },
-
- /* PCI-E Slot (Bridge) */
- Package (0x04) { 0x000EFFFF, 0x00, LNIC, 0x00 },
- Package (0x04) { 0x000EFFFF, 0x01, LNND, 0x00 },
- Package (0x04) { 0x000EFFFF, 0x02, LNIA, 0x00 },
- Package (0x04) { 0x000EFFFF, 0x03, LNIB, 0x00 },
- })
-
- Name (PR01, Package () {
- /* PIC */
- Package (0x04) { 0x0004FFFF, 0x00, LNKA, 0x00 },
- })
-
- Name (AR01, Package () {
- /* APIC */
- Package (0x04) { 0x0004FFFF, 0x00, LNIA, 0x00 },
- })
-
- Name (PR02, Package () {
- /* PIC */
- Package (0x04) { 0xFFFF, 0x00, LNKB, 0x00 },
- Package (0x04) { 0xFFFF, 0x01, LNKC, 0x00 },
- Package (0x04) { 0xFFFF, 0x02, LNKD, 0x00 },
- Package (0x04) { 0xFFFF, 0x03, LNKA, 0x00 },
- })
-
- Name (AR02, Package () {
- /* APIC */
- Package (0x04) { 0xFFFF, 0x00, LNIB, 0x00 },
- Package (0x04) { 0xFFFF, 0x01, LNIC, 0x00 },
- Package (0x04) { 0xFFFF, 0x02, LNND, 0x00 },
- Package (0x04) { 0xFFFF, 0x03, LNIA, 0x00 },
- })
-
- Name (PR03, Package () {
- /* PIC */
- Package (0x04) { 0xFFFF, 0x00, LNKA, 0x00 },
- Package (0x04) { 0xFFFF, 0x01, LNKB, 0x00 },
- Package (0x04) { 0xFFFF, 0x02, LNKC, 0x00 },
- Package (0x04) { 0xFFFF, 0x03, LNKD, 0x00 },
- })
-
- Name (AR03, Package () {
- /* APIC */
- Package (0x04) { 0xFFFF, 0x00, LNIA, 0x00 },
- Package (0x04) { 0xFFFF, 0x01, LNIB, 0x00 },
- Package (0x04) { 0xFFFF, 0x02, LNIC, 0x00 },
- Package (0x04) { 0xFFFF, 0x03, LNND, 0x00 },
- })
-
- Name (PR04, Package () {
- /* PIC */
- Package (0x04) { 0xFFFF, 0x00, LNKD, 0x00 },
- Package (0x04) { 0xFFFF, 0x01, LNKA, 0x00 },
- Package (0x04) { 0xFFFF, 0x02, LNKB, 0x00 },
- Package (0x04) { 0xFFFF, 0x03, LNKC, 0x00 },
- })
-
- Name (AR04, Package () {
- /* APIC */
- Package (0x04) { 0xFFFF, 0x00, LNND, 0x00 },
- Package (0x04) { 0xFFFF, 0x01, LNIA, 0x00 },
- Package (0x04) { 0xFFFF, 0x02, LNIB, 0x00 },
- Package (0x04) { 0xFFFF, 0x03, LNIC, 0x00 },
- })
-
- Name (PR05, Package () {
- /* PIC */
- Package (0x04) { 0xFFFF, 0x00, LNKC, 0x00 },
- Package (0x04) { 0xFFFF, 0x01, LNKD, 0x00 },
- Package (0x04) { 0xFFFF, 0x02, LNKA, 0x00 },
- Package (0x04) { 0xFFFF, 0x03, LNKB, 0x00 },
- })
-
- Name (AR05, Package () {
- /* APIC */
- Package (0x04) { 0xFFFF, 0x00, LNIC, 0x00 },
- Package (0x04) { 0xFFFF, 0x01, LNND, 0x00 },
- Package (0x04) { 0xFFFF, 0x02, LNIA, 0x00 },
- Package (0x04) { 0xFFFF, 0x03, LNIB, 0x00 },
- })
-
- /* PCI Resource Tables */
-
- Name (RSIA, ResourceTemplate () {
- /* PIC */
- IRQ (Level, ActiveLow, Shared, ) {8}
- })
-
- Name (RSMA, ResourceTemplate () {
- /* APIC */
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {16}
- })
-
- Name (RSIB, ResourceTemplate () {
- /* PIC */
- IRQ (Level, ActiveLow, Shared, ) {1}
- })
-
- Name (RSMB, ResourceTemplate () {
- /* APIC */
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {17}
- })
-
- Name (RSIC, ResourceTemplate () {
- /* PIC */
- IRQ (Level, ActiveLow, Shared, ) {2}
- })
-
- Name (RSMC, ResourceTemplate () {
- /* APIC */
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {18}
- })
-
- Name (RSND, ResourceTemplate () {
- /* PIC */
- IRQ (Level, ActiveLow, Shared, ) {13}
- })
-
- Name (RSMD, ResourceTemplate () {
- /* APIC */
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, ) {19}
- })
-
- Name (RSS2, ResourceTemplate ()
- {
- /* PIC */
- IRQ (Level, ActiveLow, Shared, )
- {3, 4, 5, 7, 9, 10, 11, 12, 14, 15}
- })
-
- Name (RSA1, ResourceTemplate ()
- {
- /* APIC */
- IRQ (Level, ActiveLow, Shared, )
- {3, 4, 5, 6, 7, 10, 11, 12, 14, 15}
- })
-
- Method (_CRS, 0, Serialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods below use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- \_SB.GXXX(node, link)
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
-#include "southbridge/nvidia/ck804/acpi/ck804.asl"
-
- /* PCI Routing Table Access */
- Method (_PRT, 0, NotSerialized) {
- If (PICM) {
- Return (AR00)
- } Else {
- Return (PR00)
- }
- }
-
- /* USB0 */
- Device (LUB0)
- {
- Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
- Name (_UID, 0x05) // _UID: Unique ID
-
- Method (_STA, 0, Serialized) {
- If (\_SB.PCI0.LPCB.INTQ) {
- Return (0xb)
- } Else {
- Return (0x9)
- }
- }
- Method (_DIS, 0, Serialized) {
- Store (0, \_SB.PCI0.LPCB.INTQ)
- }
- Method (_PRS, 0, Serialized) {
- If (PICM) {
- Return (PRSC)
- } Else {
- Return (RSA1)
- }
- }
- Method (_CRS, 0, Serialized) {
- If (PICM) {
- Return (CRSC(\_SB.PCI0.LPCB.INTQ))
- } Else {
- Return (CRSA(\_SB.PCI0.LPCB.INTQ))
- }
- }
- Method (_SRS, 1, Serialized) {
- If (PICM) {
- Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTQ)
- } Else {
- Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTQ)
- }
- }
- }
-
- /* USB2 */
- Device (LUB2)
- {
- Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
- Name (_UID, 0x07) // _UID: Unique ID
-
- Method (_STA, 0, Serialized) {
- If (\_SB.PCI0.LPCB.INTL) {
- Return (0xb)
- } Else {
- Return (0x9)
- }
- }
- Method (_DIS, 0, Serialized) {
- Store (0, \_SB.PCI0.LPCB.INTL)
- }
- Method (_PRS, 0, Serialized) {
- If (PICM) {
- Return (PRSC)
- } Else {
- Return (RSA1)
- }
- }
- Method (_CRS, 0, Serialized) {
- If (PICM) {
- Return (CRSC(\_SB.PCI0.LPCB.INTL))
- } Else {
- Return (CRSA(\_SB.PCI0.LPCB.INTL))
- }
- }
- Method (_SRS, 1, Serialized) {
- If (PICM) {
- Store (SRSC(Arg0), \_SB.PCI0.LPCB.INTL)
- } Else {
- Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTL)
- }
- }
- }
-
- /* ISA Bridge */
- Device (LKSM)
- {
- Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
- Name (_UID, 0x0C) // _UID: Unique ID
-
- Method (_STA, 0, Serialized) {
- If (\_SB.PCI0.LPCB.INTK) {
- Return (0xb)
- } Else {
- Return (0x9)
- }
- }
- Method (_DIS, 0, Serialized) {
- Store (0, \_SB.PCI0.LPCB.INTK)
- }
- Method (_PRS, 0, Serialized) {
- If (PICM) {
- Return (RSA1)
- } Else {
- Return (RSS2)
- }
- }
- Method (_CRS, 0, Serialized) {
- If (PICM) {
- Return (CRSB(\_SB.PCI0.LPCB.INTK))
- } Else {
- Return (CRSA(\_SB.PCI0.LPCB.INTK))
- }
- }
- Method (_SRS, 1, Serialized) {
- If (PICM) {
- Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTK)
- } Else {
- Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTK)
- }
- }
- }
-
- /* Bridge device link (NIC A) */
- Device (LNIA)
- {
- Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
- Name (_UID, 0x10) // _UID: Unique ID
-
- Method (_STA, 0, Serialized) {
- If (\_SB.PCI0.LPCB.INTA) {
- Return (0xb)
- } Else {
- Return (0x9)
- }
- }
- Method (_DIS, 0, Serialized) {
- Store (0, \_SB.PCI0.LPCB.INTA)
- }
- Method (_PRS, 0, Serialized) {
- If (PICM) {
- Return (RSMA)
- } Else {
- Return (RSIA)
- }
- }
- Method (_CRS, 0, Serialized) {
- If (PICM) {
- Return (CRSB(\_SB.PCI0.LPCB.INTA))
- } Else {
- Return (CRSA(\_SB.PCI0.LPCB.INTA))
- }
- }
- Method (_SRS, 1, Serialized) {
- If (PICM) {
- Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTA)
- } Else {
- Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTA)
- }
- }
- }
-
- /* Bridge device link (NIC B) */
- Device (LNIB)
- {
- Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
- Name (_UID, 0x11) // _UID: Unique ID
-
- Method (_STA, 0, Serialized) {
- If (\_SB.PCI0.LPCB.INTB) {
- Return (0xb)
- } Else {
- Return (0x9)
- }
- }
- Method (_DIS, 0, Serialized) {
- Store (0, \_SB.PCI0.LPCB.INTB)
- }
- Method (_PRS, 0, Serialized) {
- If (PICM) {
- Return (RSMB)
- } Else {
- Return (RSIB)
- }
- }
- Method (_CRS, 0, Serialized) {
- If (PICM) {
- Return (CRSB(\_SB.PCI0.LPCB.INTB))
- } Else {
- Return (CRSA(\_SB.PCI0.LPCB.INTB))
- }
- }
- Method (_SRS, 1, Serialized) {
- If (PICM) {
- Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTB)
- } Else {
- Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTB)
- }
- }
- }
-
- /* Bridge device link */
- Device (LNIC)
- {
- Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
- Name (_UID, 0x12) // _UID: Unique ID
-
- Method (_STA, 0, Serialized) {
- If (\_SB.PCI0.LPCB.INTC) {
- Return (0xb)
- } Else {
- Return (0x9)
- }
- }
- Method (_DIS, 0, Serialized) {
- Store (0, \_SB.PCI0.LPCB.INTC)
- }
- Method (_PRS, 0, Serialized) {
- If (PICM) {
- Return (RSMC)
- } Else {
- Return (RSIC)
- }
- }
- Method (_CRS, 0, Serialized) {
- If (PICM) {
- Return (CRSB(\_SB.PCI0.LPCB.INTC))
- } Else {
- Return (CRSA(\_SB.PCI0.LPCB.INTC))
- }
- }
- Method (_SRS, 1, Serialized) {
- If (PICM) {
- Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTC)
- } Else {
- Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTC)
- }
- }
- }
-
- /* Bridge device link */
- Device (LNND)
- {
- Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
- Name (_UID, 0x13) // _UID: Unique ID
-
- Method (_STA, 0, Serialized) {
- If (\_SB.PCI0.LPCB.INTD) {
- Return (0xb)
- } Else {
- Return (0x9)
- }
- }
- Method (_DIS, 0, Serialized) {
- Store (0, \_SB.PCI0.LPCB.INTD)
- }
- Method (_PRS, 0, Serialized) {
- If (PICM) {
- Return (RSMD)
- } Else {
- Return (RSND)
- }
- }
- Method (_CRS, 0, Serialized) {
- If (PICM) {
- Return (CRSB(\_SB.PCI0.LPCB.INTD))
- } Else {
- Return (CRSA(\_SB.PCI0.LPCB.INTD))
- }
- }
- Method (_SRS, 1, Serialized) {
- If (PICM) {
- Store (SRSB(Arg0), \_SB.PCI0.LPCB.INTD)
- } Else {
- Store (SRSA(Arg0), \_SB.PCI0.LPCB.INTD)
- }
- }
- }
-
- /* 0:02.0 CK804 USB 0 */
- Device (USB0)
- {
- Name (_ADR, 0x00020000) // _ADR: Address
- Name(_PRW, Package () {0x0D, 0x04}) // Wake from S1-S4
- }
-
- /* 0:02.0 CK804 USB 2 */
- Device (USB2)
- {
- Name (_ADR, 0x00020001) // _ADR: Address
- Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4
- }
-
- /* 1:04.0 VGA Controller */
- Device (VGAC)
- {
- Name (_ADR, 0x00090000) // _ADR: Address
- Name(_PRW, Package () {0x00, 0x04}) // Wake from S1-S4
- Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
- {
- If (PICM) {
- Return (AR01)
- } Else {
- Return (PR01)
- }
- }
- }
-
- /* 2:00.0 PCIe NIC A */
- Device (NICA)
- {
- Name (_ADR, 0x000B0000) // _ADR: Address
- Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
- Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
- {
- If (PICM) {
- Return (AR02)
- } Else {
- Return (PR02)
- }
- }
- Device (BDC1)
- {
- Name (_ADR, Zero) // _ADR: Address
- }
- }
-
- /* 3:00.0 PCIe NIC B */
- Device (NICB)
- {
- Name (_ADR, 0x000C0000) // _ADR: Address
- Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
- Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
- {
- If (PICM) {
- Return (AR03)
- } Else {
- Return (PR03)
- }
- }
- Device (BDC2)
- {
- Name (_ADR, Zero) // _ADR: Address
- }
- }
-
- /* 4:00.0 PCIe LSI SAS Controller */
- Device (LSIC)
- {
- Name (_ADR, 0x000D0000) // _ADR: Address
- Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
- Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
- {
- If (PICM) {
- Return (AR04)
- } Else {
- Return (PR04)
- }
- }
-
- Device (SLT2)
- {
- Name (_ADR, 0xFFFF) // _ADR: Address
- Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
- }
- }
-
- /* 5:00.0 PCIe x16 */
- Device (PCIE)
- {
- Name (_ADR, 0x000E0000) // _ADR: Address
- Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4
- Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
- {
- If (PICM) {
- Return (AR05)
- } Else {
- Return (PR05)
- }
- }
- Device (SLT1)
- {
- Name (_ADR, 0xFFFF) // _ADR: Address
- Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4
- }
- }
-
- Device (LPC) {
- Name (_HID, EisaId ("PNP0A05"))
- Name (_ADR, 0x00010000)
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Name (_CID, EisaId ("PNP030B"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, Serialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F03"))
- Name (_CID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, Serialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
-
- /* UART 1 */
- Device (URT1)
- {
- Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART
- Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f) // Always enable
- }
- Name (_PRS, ResourceTemplate() {
- StartDependentFn(0, 1) {
- IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
- IRQNoFlags() { 4 }
- } EndDependentFn()
- })
- Method (_CRS, 0)
- {
- Return(ResourceTemplate() {
- IO(Decode16, 0x3f8, 0x3f8, 0x8, 0x8)
- IRQNoFlags() { 4 }
- })
- }
- }
-
- /* UART 2 */
- Device (URT2)
- {
- Name (_HID, EisaId ("PNP0501")) // "PNP0501" for UART
- Name(_PRW, Package () {0x03, 0x04}) // Wake from S1-S4
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f) // Always enable
- }
- Name (_PRS, ResourceTemplate() {
- StartDependentFn(0, 1) {
- IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
- IRQNoFlags() { 3 }
- } EndDependentFn()
- })
- Method (_CRS, 0)
- {
- Return(ResourceTemplate() {
- IO(Decode16, 0x2f8, 0x2f8, 0x8, 0x8)
- IRQNoFlags() { 3 }
- })
- }
- }
-
- /* Floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, Serialized)
- {
- Name (BUF0, ResourceTemplate () {
- FixedIO (0x03F0, 0x08)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
- Device (HPET)
- {
- Name (_HID, EisaId ("PNP0103"))
- Name (CRS, ResourceTemplate ()
- {
- Memory32Fixed (ReadOnly,
- 0x00000000,
- 0x00001000,
- _Y02)
- IRQNoFlags () {0}
- IRQNoFlags () {8}
- })
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0F)
- }
- Method (_CRS, 0, NotSerialized)
- {
- CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._BAS, HPT1)
- CreateDWordField (CRS, \_SB.PCI0.LPC.HPET._Y02._LEN, HPT2)
- Store (SHPB, HPT1)
- Store (SHPL, HPT2)
- Return (CRS)
- }
-
- }
- }
- }
-
- Device (PWRB) { /* Start Power button device */
- Name(_HID, EISAID("PNP0C0C"))
- Name(_UID, 0xAA)
- Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
- Name(_STA, 0x0B) /* sata is invisible */
- }
- }
-
-#include "acpi/pm_ctrl.asl"
-
-}
diff --git a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c
deleted file mode 100644
index d527751eeb..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdlib.h>
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
-#include <cpu/amd/multicore.h>
-#endif
-#include <stdlib.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-/*
- * Global variables for MB layouts and these will be shared by irqtable,
- * mptable and acpi_tables.
- */
-/* busnum is default */
-unsigned char bus_ck804[6];
-unsigned apicid_ck804;
-
-/* Here you only need to set value in pci1234 for HT-IO that could be
-installed or not You may need to preset pci1234 for HTIO board, please
-refer to src/northbridge/amd/amdk8/get_pci1234.c for detail */
-static u32 pci1234x[] = {
- 0x0000ff0, 0x0000ff0, 0x0000ff0,
-};
-
-
-/* HT Chain device num, actually it is unit id base of every ht device
-in chain, assume every chain only have 4 ht device at most */
-
-static unsigned hcdnx[] = {
- 0x20202020, 0x20202020, 0x20202020,
-};
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
- unsigned apicid_base, sbdn;
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; /* Do it only once. */
-
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
- sbdn = sysconf.sbdn;
-
- for (i = 0; i < 6; i++)
- bus_ck804[i] = 0;
-
- /* CK804 */
- dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x09, 0));
- if (dev) {
- bus_ck804[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_ck804[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_ck804[2]++;
- } else {
- printk
- (BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n",
- sbdn + 0x09);
- bus_ck804[1] = 2;
- bus_ck804[2] = 3;
- }
-
- for (i = 2; i < 6; i++) {
- dev = dev_find_slot(bus_ck804[0],
- PCI_DEVFN(sbdn + 0x0b + i - 2, 0));
- if (dev) {
- bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- } else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_ck804[0], sbdn + 0x0b + i - 2);
- }
- }
-
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
- apicid_base = get_apicid_base(1);
- printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 1: apicid_base: %08x\n", apicid_base);
- } else {
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 0: apicid_base: %08x\n", apicid_base);
- }
- apicid_ck804 = apicid_base + 0;
-}
diff --git a/src/mainboard/asus/kfsn4-dre_k8/irq_tables.c b/src/mainboard/asus/kfsn4-dre_k8/irq_tables.c
deleted file mode 100644
index d06980c773..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/irq_tables.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- *
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-// WARNING
-// These tables are INVALID for this mainboard!
-// The ACPI tables are correct; a backport to these PIR tables is needed...
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_isa;
-extern unsigned char bus_ck804[6];
-
-
-/**
- * Add one line to IRQ table.
- */
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
- uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2,
- uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-/**
- * Create the IRQ routing table.
- * Values are derived from getpir generated code.
- */
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num, sbdn;
- uint8_t *v, sum = 0;
- int i;
-
- /* get_bus_conf() will find out all bus num and APIC that share with
- * mptable.c and mptable.c.
- */
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be between 0xf0000 & 0x100000. */
- printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *)(addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
- pirq->rtr_bus = bus_ck804[0];
- pirq->rtr_devfn = ((sbdn + 9) << 3) | 0;
- pirq->exclusive_irqs = 0x828;
- pirq->rtr_vendor = 0x10de;
- pirq->rtr_device = 0x005c;
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *)(&pirq->checksum + 1);
- slot_num = 0;
-
- /* Slot1 PCIE 16x */
- write_pirq_info(pirq_info, bus_ck804[1], (0 << 3) | 0, 0x3, 0xdeb8, 0x4,
- 0xdeb8, 0x1, 0xdeb8, 0x2, 0xdeb8, 4, 0);
- pirq_info++;
- slot_num++;
-
-
- /* Slot2 PCIE 1x */
- write_pirq_info(pirq_info, bus_ck804[2], (0 << 3) | 0, 0x4, 0xdeb8, 0x1,
- 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 5, 0);
- pirq_info++;
- slot_num++;
-
- /* Slot3 PCIE 1x */
- write_pirq_info(pirq_info, bus_ck804[3], (0 << 3) | 0, 0x1, 0xdeb8, 0x2,
- 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 6, 0);
- pirq_info++;
- slot_num++;
-
- /* Slot4 PCIE 4x */
- write_pirq_info(pirq_info, bus_ck804[4], (0x4 << 3) | 0, 0x2,
- 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0x1, 0xdeb8, 7, 0);
- pirq_info++;
- slot_num++;
-
- /* Slot5 - Slot7 PCI */
- for (i = 0; i < 3; i++) {
- write_pirq_info(pirq_info, bus_ck804[5], (0 << (6 + i)) | 0,
- ((i + 0) % 4) + 1, 0xdeb8,
- ((i + 1) % 4) + 1, 0xdeb8,
- ((i + 2) % 4) + 1, 0xdeb8,
- ((i + 3) % 4) + 1, 0xdeb8, i, 0);
- pirq_info++;
- slot_num++;
- }
-
- /* PCI bridge */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 9) << 3) | 0, 0x1,
- 0xdeb8, 0x2, 0xdeb8, 0x3, 0xdeb8, 0x4, 0xdeb8, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* SMBus */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 1) << 3) | 0, 0x2,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* USB */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 2) << 3) | 0, 0x1,
- 0xdeb8, 0x2, 0xdeb8, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* SATA */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 7) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- /* SATA */
- write_pirq_info(pirq_info, bus_ck804[0], ((sbdn + 8) << 3) | 0, 0x1,
- 0xdeb8, 0, 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
- if (sum != pirq->checksum)
- pirq->checksum = sum;
-
- printk(BIOS_INFO, "done.\n");
-
- return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/asus/kfsn4-dre_k8/mptable.c b/src/mainboard/asus/kfsn4-dre_k8/mptable.c
deleted file mode 100644
index efa583c47f..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/mptable.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- * Copyright (C) 2007 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-// WARNING
-// These tables are INCOMPLETE for this mainboard!
-// The ACPI tables are correct; a backport to these MP tables is needed...
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-extern unsigned char bus_ck804[6];
-extern unsigned apicid_ck804;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- unsigned sbdn;
- int bus_isa;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- {
- struct device *dev;
- struct resource *res;
-
- dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res) {
- smp_write_ioapic(mc, apicid_ck804, 0x11,
- res2mmio(res, 0, 0));
- }
-
- /* Initialize interrupt mapping. */
-
- /*
- LPC bridge PCI config registers:
-
- 0x7c:0x0000ffff
- - bitmap of masked pci irqs?
- - PIRQ[ABCD] possibly?
-
- 0x7c:0x00f00000
- - sata at f8 - port 1
-
- 0x7c:0x0f000000
- - sata at f7 - port 1
-
- 0x80:0xf0000000
- - sata at f7 - port 0
-
- 0x80:0x0f000000
- - sata at f8 - port 0
-
- 0x80:0x0000f000
- - EHCI
-
- 0x84:0x00000f00
- - NIC
-
- 0x84:0x0000000f
- - OHCI
-
- known values of nibbles:
-
- 0 - unrouted?
- 1 - irq 23
- 8 - irq 20
- c - irq 12
- d - irq 21
- e - irq 14
- f - irq 15
- */
-
- // Enable interrupts for commonly used devices (USB, SATA, etc.)
- pci_write_config32(dev, 0x7c, 0x0d800018);
- pci_write_config32(dev, 0x80, 0xd8002009);
- pci_write_config32(dev, 0x84, 0x00000001);
- }
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
-
- // Onboard ck804 smbus
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804,
- 0xa);
-
- // Onboard ck804 USB 1.1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804,
- 0x15);
-
- // Onboard ck804 USB 2
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804,
- 0x14);
-
- // Onboard ck804 SATA 0
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804,
- 0x17);
-
- // Onboard ck804 SATA 1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
- bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804,
- 0x16);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, bus_ck804[0]);
-
- /* There is no extension information... */
-
- /* Compute the checksums. */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c b/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c
deleted file mode 100644
index cfbade68f2..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
-
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [31:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> Nvidia CK 804 */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independent of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> Nvidia CK 804 */
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
-
- };
-
- int max;
- max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c
deleted file mode 100644
index a404b06ad3..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c
+++ /dev/null
@@ -1,362 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-unsigned int get_sbdn(unsigned bus);
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <timestamp.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/nvidia/ck804/early_smbus.h"
-#include <reset.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include <cbmem.h>
-#include <delay.h>
-
-#include <cpu/amd/mtrr.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627thg/w83627thg.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <northbridge/amd/amdk8/f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <spd.h>
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-#define CK804_MB_SETUP \
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/
-
-#include <southbridge/nvidia/ck804/early_setup_ss.h>
-#include "southbridge/nvidia/ck804/early_setup_car.c"
-#include <cpu/amd/microcode.h>
-
-#define GPIO3_DEV PNP_DEV(0x2e, W83627THG_GPIO3)
-
-/**
- * @brief Get SouthBridge device number
- * @param[in] bus target bus number
- * @return southbridge device number
- */
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus);
- return (dev >> 15) & 0x1f;
-}
-
-/*
- * ASUS KFSN4-DRE specific SPD enable/disable magic.
- *
- * Setting CK804 GPIO43 and GPIO44 to 0 and 0 respectively will make the
- * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD
- * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which
- * will make RAM init fail.
- *
- * Disable SPD access after RAM init to allow access to standard SMBus/I2C offsets
- * which is required e.g. by lm-sensors.
- */
-
-#define CK804_BOARD_BOOT_BASE_UNIT_UID 1
-
-static const unsigned int ctrl_conf_enable_spd_node0[] = {
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/
-};
-
-static const unsigned int ctrl_conf_enable_spd_node1[] = {
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x00),/* W2,GPIO43, U6 input S0*/
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x01),/* W3,GPIO44, U6 input S1*/
-};
-
-static const unsigned int ctrl_conf_disable_spd[] = {
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+42, ~(0x0f),(0x04 | 0x01),/* W2,GPIO43, U6 input S0*/
- RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+43, ~(0x0f),(0x04 | 0x00),/* W3,GPIO44, U6 input S1*/
-};
-
-static const unsigned int ctrl_conf_fix_pci_numbering[] = {
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0x44), ~(0x00010000), 0x00000000, /* Force CK804 to start its internal device numbering (Base Unit ID) at 0 instead of the power-on default of 1 */
-};
-
-static const unsigned int ctrl_conf_enable_msi_mapping[] = {
- RES_PCI_IO, PCI_ADDR(0, 0, 0, 0xe0), ~(0x00000000), 0x00010000, /* Enable MSI mapping on host bridge -- without this Linux cannot use the network device MSI interrupts! */
-};
-
-static void ck804_control(const unsigned int* values, u32 size, uint8_t bus_unit_id)
-{
- unsigned busn[4], io_base[4];
- int i, ck804_num = 0;
-
- for (i = 0; i < 4; i++) {
- u32 id;
- pci_devfn_t dev;
- if (i == 0) /* SB chain */
- dev = PCI_DEV(i * 0x40, bus_unit_id, 0);
- else
- dev = 0;
- id = pci_read_config32(dev, PCI_VENDOR_ID);
- if (id == 0x005e10de) {
- busn[ck804_num] = i * 0x40;
- io_base[ck804_num] = i * 0x4000;
- ck804_num++;
- }
- }
-
- if (ck804_num < 1)
- printk(BIOS_WARNING, "CK804 not found at device base unit id %02x!\n", bus_unit_id);
-
- ck804_early_set_port(ck804_num, busn, io_base);
-
- setup_resource_map_x_offset(values,
- size,
- PCI_DEV(0, bus_unit_id, 0), io_base[0]);
-
- ck804_early_clear_port(ck804_num, busn, io_base);
-}
-
-static void sio_setup(void)
-{
- u32 dword;
- u8 byte;
-
- /* Subject decoding */
- byte = pci_read_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b);
- byte |= 0x20;
- pci_write_config8(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0x7b, byte);
-
- /* LPC Positive Decode 0 */
- dword = pci_read_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0);
- /* Serial 0, Serial 1 */
- dword |= (1 << 0) | (1 << 1);
- pci_write_config32(PCI_DEV(0, CK804_BOARD_BOOT_BASE_UNIT_UID + 1, 0), 0xa0, dword);
-}
-
-static const uint16_t spd_addr[] = {
- // Node 0
- RC00 | DIMM0, RC00 | DIMM2, RC00 | DIMM4, RC00 | DIMM6, RC00 | DIMM1, RC00 | DIMM3, RC00 | DIMM5, RC00 | DIMM7,
- // Node 1
- RC01 | DIMM0, RC01 | DIMM2, RC01 | DIMM4, RC01 | DIMM6, RC01 | DIMM1, RC01 | DIMM3, RC01 | DIMM5, RC01 | DIMM7,
-};
-
-void activate_spd_rom(const struct mem_controller *ctrl)
-{
- printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id);
- if (ctrl->node_id == 0) {
- printk(BIOS_DEBUG, "enable_spd_node0()\n");
- ck804_control(ctrl_conf_enable_spd_node0, ARRAY_SIZE(ctrl_conf_enable_spd_node0), CK804_DEVN_BASE);
- }
- else if (ctrl->node_id == 1) {
- printk(BIOS_DEBUG, "enable_spd_node1()\n");
- ck804_control(ctrl_conf_enable_spd_node1, ARRAY_SIZE(ctrl_conf_enable_spd_node1), CK804_DEVN_BASE);
- }
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- struct sys_info *sysinfo = &sysinfo_car;
-
- uint32_t bsp_apicid = 0;
- uint32_t dword;
- uint8_t needs_reset = 0;
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- struct cpuid_result cpuid1;
-#endif
-
- timestamp_init(timestamp_get());
- timestamp_add_now(TS_START_ROMSTAGE);
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
- sio_setup();
- }
-
- post_code(0x30);
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- post_code(0x32);
-
- winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- if (CONFIG_MAX_PHYSICAL_CPUS != 2)
- printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket board!\n", CONFIG_MAX_PHYSICAL_CPUS);
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- dword = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", dword);
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- /* Setup sysinfo defaults */
- set_sysinfo_in_ram(0);
-
- post_code(0x33);
-
- setup_coherent_ht_domain();
- post_code(0x35);
-
- /* Wait for all base cores to start */
- wait_all_core0_started();
- post_code(0x36);
-
- /* Setup any mainboard PCI settings etc. */
- setup_mb_resource_map();
- post_code(0x37);
-
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
- /* Core0 on each node is configured. Now setup any additional cores. */
- printk(BIOS_DEBUG, "start_other_cores()\n");
- start_other_cores();
- post_code(0x38);
- wait_all_other_cores_started(bsp_apicid);
- post_code(0x39);
- }
-
- ht_setup_chains_x(sysinfo);
-
-#if IS_ENABLED(CONFIG_SET_FIDVID)
- /* Check to see if processor is capable of changing FIDVID */
- /* otherwise it will throw a GP# when reading FIDVID_STATUS */
- cpuid1 = cpuid(0x80000007);
- if ((cpuid1.edx & 0x6) == 0x6) {
- msr_t msr;
-
- /* Read FIDVID_STATUS */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
-
- enable_fid_change();
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
- init_fidvid_bsp(bsp_apicid);
-
- /* Show final FID and VID */
- msr = rdmsr(0xc0010042);
- printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
- } else {
- printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
- }
-#endif
-
- init_timer(); /* Need to use TMICT to synchronize FID/VID. */
-
- printk(BIOS_DEBUG, "set_ck804_base_unit_id()\n");
- ck804_control(ctrl_conf_fix_pci_numbering, ARRAY_SIZE(ctrl_conf_fix_pci_numbering), CK804_BOARD_BOOT_BASE_UNIT_UID);
-
- post_code(0x3a);
-
- printk(BIOS_DEBUG, "optimize_link_coherent_ht()\n");
- needs_reset = optimize_link_coherent_ht();
- printk(BIOS_DEBUG, "optimize_link_incoherent_ht()\n");
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- printk(BIOS_DEBUG, "ck804_early_setup_x()\n");
- needs_reset |= ck804_early_setup_x();
-
- /* FIDVID change will issue one LDTSTOP and the HT change will be effective too */
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
-
- post_code(0x3b);
-
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl in sysinfo now; */
- printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
- post_code(0x3d);
-
- printk(BIOS_DEBUG, "enable_smbus()\n");
- enable_smbus();
-
-#if 0
- /* FIXME
- * After the AMD K10 code has been converted to use
- * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block
- */
- if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {
- dump_spd_registers(&cpu[0]);
- dump_smbus_registers();
- }
-#endif
-
- post_code(0x40);
-
- timestamp_add_now(TS_BEFORE_INITRAM);
- printk(BIOS_DEBUG, "sdram_initialize()\n");
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
- timestamp_add_now(TS_AFTER_INITRAM);
-
- cbmem_initialize_empty();
- post_code(0x41);
-
- printk(BIOS_DEBUG, "disable_spd()\n");
- ck804_control(ctrl_conf_disable_spd, ARRAY_SIZE(ctrl_conf_disable_spd), CK804_DEVN_BASE);
-
- printk(BIOS_DEBUG, "enable_msi_mapping()\n");
- ck804_control(ctrl_conf_enable_msi_mapping, ARRAY_SIZE(ctrl_conf_enable_msi_mapping), CK804_DEVN_BASE);
-
- /* Initialize GPIO */
- /* Access SuperIO GPI03 logical device */
- uint16_t port = GPIO3_DEV >> 8;
- outb(0x87, port);
- outb(0x87, port);
- pnp_set_logical_device(GPIO3_DEV);
- /* Set GP37 (power LED) to output */
- pnp_write_config(GPIO3_DEV, 0xf0, 0x7f);
- /* Set GP37 (power LED) on */
- pnp_write_config(GPIO3_DEV, 0xf1, 0x80);
- /* Set pin 64 multiplex to GP37 */
- uint8_t cr2c = pnp_read_config(GPIO3_DEV, 0x2c);
- pnp_write_config(GPIO3_DEV, 0x2c, (cr2c & 0xf3) | 0x04);
- /* Restore default SuperIO access */
- outb(0xaa, port);
-}
diff --git a/src/mainboard/asus/kfsn4-dre_k8/spd_notes.txt b/src/mainboard/asus/kfsn4-dre_k8/spd_notes.txt
deleted file mode 100644
index 9287a5f75a..0000000000
--- a/src/mainboard/asus/kfsn4-dre_k8/spd_notes.txt
+++ /dev/null
@@ -1,69 +0,0 @@
-====================================================================================================
-SPD mux
-====================================================================================================
-
-DIMM_A1 SDA signal traced to U6 pin 1
-Destructive testing of failed board (removal of U7 northbridge!) yielded the following information:
-U6 S0 <--> U7 W2
-U6 S1 <--> U7 W3
-
-Proprietary BIOS enables the SPD during POST with:
-S0: LOW
-S1: LOW
-
-then temporarily switches to:
-S0: LOW
-S1: HIGH
-
-then switches to runtime mode with:
-S0: HIGH
-S1: LOW
-
-After probing with a custom GPIO-flipping tool under Linux the following GPIO mappings were found:
-CK804 pin W2 <--> GPIO43
-CK804 pin W3 <--> GPIO44
-
-====================================================================================================
-W83793 (U46)
-====================================================================================================
-
-Sensor mappings:
-FRNT_FAN1: FAN3
-FRNT_FAN2: FAN4
-FRNT_FAN3: FAN5
-FRNT_FAN4: FAN6
-FRNT_FAN5: FAN9
-FRNT_FAN6: FAN10
-REAR_FAN1: FAN7
-REAR_FAN2: FAN8
-REAR_FAN3: FAN11
-REAR_FAN4: FAN12
-
-====================================================================================================
-Other hardware
-====================================================================================================
-
-Power LED (-) is connected to U15 (SuperIO) pin 64 via U4 pins 5,6 and a small MOSFET
-ID LED (-) is connected to a ??? via U4 pins 1,2,3,4 and U77 pins 5,6
-It appears that setting U15 (SuperIO) pin 88 LOW will override the ID LED and force it ON
-
-RECOVERY2 middle pin is connected to U15 (SuperIO) pin 89
-Normal is HIGH, recovery is LOW.
-
-PCIe slot WAKE# connects to U7 pin E23 (PCIE_WAKE#)
-
-CPU_WARN1 is driven by (???) via a simple buffer (U13 pin 10)
-MEM_WARN1 is driven by U7 pin AD3 (CPUVDD_EN) via a simple buffer (U101 pin 3)
-
-U7 pin AK3 is disconnected (routed to unpopulated capacitor/resistor)
-PU1 pin 37 (VDDPWRGD) drives U7 pin AJ4 (CPU_VLD)
-A small MOSFET directly above another small MOSFET directly above the right-hand edge of the PCIe slot drives U7 pin AK5 (HT_VLD)
-
-When > Barcelona CPU installed on PCB rev 1.04G:
-U7 pin AK4 (MEM_VLD): HIGH
-PU1 pin 37: LOW
-U7 pin AK5: LOW
-
-HyperTransport 1.2V supply appears to be generated by a linear regulator containing Q191 and downconverting the CK804 1.5V supply
-The enable pin appears to be tied to AUX_PANEL pin 1 (+5VSB) via a resistor
-Through two MOSFETs the HT supply enable pin is tied to U7 pin AE3 (HTVDD_EN)
diff --git a/src/mainboard/asus/m2n-e/Kconfig b/src/mainboard/asus/m2n-e/Kconfig
deleted file mode 100644
index 7cb903bb93..0000000000
--- a/src/mainboard/asus/m2n-e/Kconfig
+++ /dev/null
@@ -1,77 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-if BOARD_ASUS_M2N_E
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_AM2
- select DIMM_DDR2
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_NVIDIA_MCP55
- select HT_CHAIN_DISTRIBUTE
- select MCP55_USE_NIC
- select MCP55_USE_AZA
- select SUPERIO_ITE_IT8716F
- select SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
- select PARALLEL_CPU_INIT
- select HAVE_OPTION_TABLE
- select HAVE_MP_TABLE
- select LIFT_BSP_APIC_ID
- select BOARD_ROMSIZE_KB_512
- select K8_ALLOCATE_IO_RANGE
-
-config MAINBOARD_DIR
- string
- default asus/m2n-e
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x08000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MEM_TRAIN_SEQ
- int
- default 2
-
-config MAINBOARD_PART_NUMBER
- string
- default "M2N-E"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-endif # BOARD_ASUS_M2N_E
diff --git a/src/mainboard/asus/m2n-e/Kconfig.name b/src/mainboard/asus/m2n-e/Kconfig.name
deleted file mode 100644
index e3cbc5da00..0000000000
--- a/src/mainboard/asus/m2n-e/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_M2N_E
- bool "M2N-E"
diff --git a/src/mainboard/asus/m2n-e/Makefile.inc b/src/mainboard/asus/m2n-e/Makefile.inc
deleted file mode 100644
index 94559573a7..0000000000
--- a/src/mainboard/asus/m2n-e/Makefile.inc
+++ /dev/null
@@ -1,17 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ramstage-$(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) += fanctl.c
diff --git a/src/mainboard/asus/m2n-e/board_info.txt b/src/mainboard/asus/m2n-e/board_info.txt
deleted file mode 100644
index d7b04de6d1..0000000000
--- a/src/mainboard/asus/m2n-e/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: desktop
-Board URL: http://www.asus.com/Motherboards/AMD_AM2/M2NE/
-ROM package: PLCC
-ROM protocol: LPC
-ROM socketed: y
-Flashrom support: y
-Release year: 2006
diff --git a/src/mainboard/asus/m2n-e/cmos.layout b/src/mainboard/asus/m2n-e/cmos.layout
deleted file mode 100644
index 95b7de3a6e..0000000000
--- a/src/mainboard/asus/m2n-e/cmos.layout
+++ /dev/null
@@ -1,68 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 200Mhz
-8 1 166Mhz
-8 2 133Mhz
-8 3 100Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/m2n-e/devicetree.cb b/src/mainboard/asus/m2n-e/devicetree.cb
deleted file mode 100644
index 5938684899..0000000000
--- a/src/mainboard/asus/m2n-e/devicetree.cb
+++ /dev/null
@@ -1,117 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # (L)APIC cluster
- chip cpu/amd/socket_AM2 # CPU socket
- device lapic 0 on end # Local APIC of the CPU
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x1043 0x8239 inherit
- chip northbridge/amd/amdk8 # Northbridge / RAM controller
- device pci 18.0 on # Link 0 == LDT 0
- chip southbridge/nvidia/mcp55 # Southbridge
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/ite/it8716f # Super I/O
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 off # Com2 (N/A)
- end
- device pnp 2e.3 on # Parallel port
- io 0x60 = 0x378
- io 0x62 = 0x000
- irq 0x70 = 7
- drq 0x74 = 4
- end
- device pnp 2e.4 on # Environment controller
- io 0x60 = 0x290
- io 0x62 = 0x000
- irq 0x70 = 0
- end
- device pnp 2e.5 on # PS/2 keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1 # PS/2 keyboard IRQ
- end
- device pnp 2e.6 on # PS/2 mouse
- irq 0x70 = 12 # PS/2 mouse IRQ
- end
- device pnp 2e.7 off # GPIO
- io 0x60 = 0x0000 # SMI# Normal Run Access
- io 0x62 = 0x800 # Simple I/O
- io 0x64 = 0x0000 # Serial Flash I/F
- end
- device pnp 2e.8 off # MIDI (N/A)
- end
- device pnp 2e.9 off # Game port (N/A)
- end
- device pnp 2e.a off # Consumer IR (N/A)
- end
- end
- end
- device pci 1.1 on # SM 0
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- end
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # IDE
- device pci 5.0 on end # SATA 0
- device pci 5.1 on end # SATA 1
- device pci 5.2 on end # SATA 2
- device pci 6.0 on end # PCI
- device pci 6.1 on end # Azalia (HD Audio)
- device pci 8.0 on end # NIC
- device pci 9.0 off end # NIC (N/A)
- device pci a.0 on end # PCI E 5 (PCIEX4)
- device pci b.0 off end # PCI E 4
- device pci c.0 on end # PCI E 3 (PCIEX1_2)
- device pci d.0 on end # PCI E 2 (PCIEX1_1)
- device pci e.0 off end # PCI E 1
- device pci f.0 on end # PCI E 0 (PCIEX16_1)
- register "ide0_enable" = "1" # Primary IDE
- register "ide1_enable" = "0" # Secondary IDE (N/A)
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
- end
- end
- device pci 18.0 on end # Link 1
- device pci 18.0 on end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/asus/m2n-e/fanctl.c b/src/mainboard/asus/m2n-e/fanctl.c
deleted file mode 100644
index 8fa7d82578..0000000000
--- a/src/mainboard/asus/m2n-e/fanctl.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * The ASUS M2N-E has 6 different fans, connected to two different chips:
- * - ITE IT8716F: fan1 = CPU_FAN, fan2 = CHA_FAN1, fan3 = PWR_FAN1
- * - Analog Devices ADT7475: fan1 = CHA_FAN4, fan2 = CHA_FAN2, fan3 = CHA_FAN3
- */
-
-#include <arch/io.h>
-#include <stdlib.h>
-#include <superio/ite/it8716f/it8716f.h>
-
-static void write_index(u16 port, u8 reg, u8 value)
-{
- outb(reg, port);
- outb(value, port + 1);
-}
-
-static const struct {
- u8 index;
- u8 value;
-} sequence[] = {
- /* Enable startup of monitoring operations. */
- { 0x00, 0x11},
- /* Polarity active-high, PWM frequency 23.43KHz, activate fans 1-3. */
- { 0x14, 0xd7},
- /* Set the correct sensor types. TMPIN1: diode, TMPIN2/3: resistor. */
- { 0x51, 0x31},
- /* Fan1 (CPU_FAN) is software-controlled. */
- { 0x15, 0x7f},
- /* Fan2 (CHA_FAN1) is software-controlled. */
- { 0x16, 0x7f},
- /* Fan3 (PWR_FAN1) is software-controlled. */
- { 0x17, 0x7f},
- /* Enable fan1/2/3, select "on/off mode" for all of them. */
- { 0x13, 0x70},
-};
-
-/* Called from src/ite/it8716f/superio.c. */
-void init_ec(u16 base)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(sequence); i++)
- write_index(base, sequence[i].index, sequence[i].value);
-}
diff --git a/src/mainboard/asus/m2n-e/get_bus_conf.c b/src/mainboard/asus/m2n-e/get_bus_conf.c
deleted file mode 100644
index 6809eda4a9..0000000000
--- a/src/mainboard/asus/m2n-e/get_bus_conf.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/multicore.h>
-#include <cpu/amd/amdk8_sysconf.h>
-#include <stdlib.h>
-
-/* Global variables for MB layouts (shared by irqtable/mptable/acpi_table). */
-// busnum is default.
-unsigned char bus_mcp55[8]; // 1
-unsigned apicid_mcp55;
-
-unsigned pci1234x[] = {
- /* Here you only need to set value in pci1234 for HT-IO that could
- * be installed or not. You may need to preset pci1234 for HTIO board,
- * please refer to * src/northbridge/amd/amdk8/get_sblk_pci1234.c.
- */
- 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-
-unsigned hcdnx[] = {
- /* HT Chain device num, actually it is unit id base of every ht
- * device in chain, assume every chain only have 4 ht device at most.
- */
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
-{
- unsigned int apicid_base, sbdn;
- struct device *dev;
- int i;
-
- if (get_bus_conf_done == 1)
- return; /* Do it only once. */
-
- get_bus_conf_done = 1;
-
- sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); /* First byte of first chain */
- sbdn = sysconf.sbdn;
-
- for (i = 0; i < 8; i++)
- bus_mcp55[i] = 0;
-
- bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
-
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06, 0));
- if (dev) {
- bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_mcp55[2]++;
- } else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, "
- "using defaults\n", sbdn + 0x06);
- bus_mcp55[1] = 2;
- bus_mcp55[2] = 3;
- }
-
- for (i = 2; i < 8; i++) {
- dev = dev_find_slot(bus_mcp55[0],
- PCI_DEVFN(sbdn + 0x0a + i - 2, 0));
- if (dev)
- bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
-
- if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
- apicid_base = get_apicid_base(1);
- else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
- apicid_mcp55 = apicid_base + 0;
-}
diff --git a/src/mainboard/asus/m2n-e/hda_verb.c b/src/mainboard/asus/m2n-e/hda_verb.c
deleted file mode 100644
index 3c82ba84e0..0000000000
--- a/src/mainboard/asus/m2n-e/hda_verb.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * HDA codec soldered onto the ASUS M2N-E:
- * Analog Devices AD1988B (High Definition Audio SoundMAX Codec), rev. 0x100200
- * http://www.analog.com/static/imported-files/data_sheets/AD1988A_1988B.pdf
- */
-
-#include <device/azalia_device.h>
-
-const u32 cim_verb_data[] = {
- /* coreboot specific header */
- 0x11d4198b, /* Codec Vendor / Device ID: Analog Devices AD1988B */
- 0x104381f6, /* Subsystem ID (0x1043 == ASUS) */
- 0x0000000d, /* Number of "pin complex" entries in the table */
-
- /* NID 0x01, FUNCTION, Designates this device as an audio codec */
- /* Set the Implementation ID (IID), here: 0x104381f6. */
- AZALIA_SUBVENDOR(0x0, 0x104381f6),
-
- /* "Pin complex" HDA widgets. Comments: Node ID, Name, Description. */
-
- /* NID 0x11, Port A, Front panel headphone jack */
- AZALIA_PIN_CFG(0x0, 0x11, 0x02214130),
-
- /* NID 0x12, Port D, Rear panel front speaker jack */
- AZALIA_PIN_CFG(0x0, 0x12, 0x01014010),
-
- /* NID 0x13, MONO_OUT, Monaural output pin */
- AZALIA_PIN_CFG(0x0, 0x13, 0x511711f0),
-
- /* NID 0x14, Port B, Front panel microphone jack */
- AZALIA_PIN_CFG(0x0, 0x14, 0x02a19122),
-
- /* NID 0x15, Port C, Rear panel line-in jack */
- AZALIA_PIN_CFG(0x0, 0x15, 0x01813021),
-
- /* NID 0x16, Port F, Rear panel surround-back (5.1) jack */
- AZALIA_PIN_CFG(0x0, 0x16, 0x01011012),
-
- /* NID 0x17, Port E, Rear panel microphone jack */
- AZALIA_PIN_CFG(0x0, 0x17, 0x01a19020),
-
- /* NID 0x18, CD IN, Analog CD input */
- AZALIA_PIN_CFG(0x0, 0x18, 0x9933112e),
-
- /* NID 0x1a, Analog PCBEEP, External analog PCBEEP signal input */
- AZALIA_PIN_CFG(0x0, 0x1a, 0x99f301f0),
-
- /* NID 0x1b, S/PDIF Out, S/PDIF output pin */
- AZALIA_PIN_CFG(0x0, 0x1b, 0x0145f1f0),
-
- /* NID 0x1c, S/PDIF In, S/PDIF input pin */
- AZALIA_PIN_CFG(0x0, 0x1c, 0x41c5f1f0),
-
- /* NID 0x24, Port G, Rear panel C/LFE jack */
- AZALIA_PIN_CFG(0x0, 0x24, 0x01016011),
-
- /* NID 0x25, Port H, Rear panel surround-side (7.1) jack */
- AZALIA_PIN_CFG(0x0, 0x25, 0x01012014),
-};
-
-const u32 pc_beep_verbs[0] = {};
-
-AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c
deleted file mode 100644
index 5d9f0fc400..0000000000
--- a/src/mainboard/asus/m2n-e/mptable.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-#define PCI_INT(bus, dev, fn, pin) \
- smp_write_intsrc(mc, mp_INT, \
- MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, \
- bus_mcp55[bus], (((dev) << 2) | (fn)), apicid_mcp55, (pin))
-
-extern unsigned char bus_mcp55[8];
-extern unsigned apicid_mcp55;
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- unsigned int sbdn;
- int i, j, bus_isa;
- struct device *dev;
- struct resource *res;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
-
- get_bus_conf();
- sbdn = sysconf.sbdn;
-
- mptable_write_buses(mc, NULL, &bus_isa);
-
- dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x1, 0));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_1);
- if (res)
- smp_write_ioapic(mc, apicid_mcp55, 0x11,
- res2mmio(res, 0, 0));
-
- pci_write_config32(dev, 0x7c, 0x00000000);
- pci_write_config32(dev, 0x80, 0x11002009);
- pci_write_config32(dev, 0x84, 0x2000dd08);
- }
-
- mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0);
-
- /* I/O Ints */
- PCI_INT(0, sbdn + 1, 1, 10); /* SMBus */
- PCI_INT(0, sbdn + 2, 0, 20); /* USB 1.1 */
- PCI_INT(0, sbdn + 2, 1, 22); /* USB 2.0 */
- PCI_INT(0, sbdn + 4, 0, 14); /* IDE */
- PCI_INT(0, sbdn + 5, 0, 23); /* SATA 0 */
- PCI_INT(0, sbdn + 5, 1, 23); /* SATA 1 */
- PCI_INT(0, sbdn + 5, 2, 22); /* SATA 2 */
- PCI_INT(0, sbdn + 6, 1, 21); /* HD audio */
- PCI_INT(0, sbdn + 8, 0, 24); /* NIC */
-
- /* PCI-E slots (two x1, one x4, one x16) */
- for (j = 7; j >= 2; j--) {
- if (!bus_mcp55[j])
- continue;
- for (i = 0; i < 4; i++)
- PCI_INT(j, 0, i, 0x10 + (2 + j + i + 4 - sbdn % 4) % 4);
- }
-
- /* PCI slots (three on this board) */
- for (j = 0; j < 3; j++) {
- for (i = 0; i < 4; i++)
- PCI_INT(1, 0x06 + j, i, 0x10 + (2 + i + j) % 4);
- }
-
- /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, bus_isa);
-
- /* Compute the checksums. */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/m2n-e/resourcemap.c b/src/mainboard/asus/m2n-e/resourcemap.c
deleted file mode 100644
index 57e7389490..0000000000
--- a/src/mainboard/asus/m2n-e/resourcemap.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
-
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
-// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration region i
- */
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
-
- };
-
- int max = ARRAY_SIZE(register_values);
- setup_resource_map(register_values, max);
-}
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
deleted file mode 100644
index 329a95e4d7..0000000000
--- a/src/mainboard/asus/m2n-e/romstage.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <southbridge/nvidia/mcp55/mcp55.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-#include <lib.h>
-#include <spd.h>
-#include <cpu/x86/lapic.h>
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8716f/it8716f.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
-#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO)
-
-unsigned get_sbdn(unsigned bus);
-
-unsigned get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- /* Find the device. */
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
- PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
-
- return (dev >> 15) & 0x1f;
-}
-
-void memreset(int controllers, const struct mem_controller *ctrl) {}
-void activate_spd_rom(const struct mem_controller *ctrl) {}
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include <northbridge/amd/amdk8/f.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include <southbridge/nvidia/mcp55/early_setup_ss.h>
-#include "southbridge/nvidia/mcp55/early_setup_car.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-/* FIXME
- * Dummy method to allow build
- * Determine if this board / CPU should support
- * FID/VID and implement proper support if so
- */
-#if IS_ENABLED(CONFIG_SET_FIDVID)
-void init_fidvid_ap(u32 bsp_apicid, u32 apicid) { }
-#endif
-
-static void sio_setup(void)
-{
- u8 byte;
- u32 dword;
- pci_devfn_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */
-
- /* Subject decoding */
- byte = pci_read_config8(dev, 0x7b);
- byte |= (1 << 5);
- pci_write_config8(dev, 0x7b, byte);
-
- /* LPC Positive Decode 0 */
- dword = pci_read_config32(dev, 0xa0);
- dword |= (1 << 0); /* COM1 */
- pci_write_config32(dev, 0xa0, dword);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const u16 spd_addr[] = {
- DIMM0, DIMM2, 0, 0, /* Channel A (DIMM_A1, DIMM_A2) */
- DIMM1, DIMM3, 0, 0, /* Channel B (DIMM_B1, DIMM_B2) */
- };
-
- struct sys_info *sysinfo = &sysinfo_car;
- int needs_reset = 0;
- unsigned bsp_apicid = 0;
-
- if (!cpu_init_detectedx && boot_cpu()) {
- /* Allow the HT devices to be found. */
- enumerate_ht_chain();
- sio_setup();
- }
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- setup_mb_resource_map();
- report_bist_failure(bist);
- console_init();
-
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo, sysinfo + 1);
- printk(BIOS_DEBUG, "bsp_apicid=0x%02x\n", bsp_apicid);
-
- /* In BSP so could hold all AP until sysinfo is in RAM. */
- set_sysinfo_in_ram(0);
-
- setup_coherent_ht_domain(); /* Routing table and start other core0. */
- wait_all_core0_started();
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /*
- * It is said that we should start core1 after all core0 launched
- * becase optimize_link_coherent_ht is moved out from
- * setup_coherent_ht_domain, so here need to make sure last core0 is
- * started, esp for two way system (there may be APIC ID conflicts in
- * that case).
- */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- /* Set up chains and store link pair for optimization later. */
- ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
-
- /* TODO: FIDVID */
-
- init_timer(); /* Need to use TMICT to synchronize FID/VID. */
-
- needs_reset |= optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- needs_reset |= mcp55_early_setup_x();
-
- /*
- * FIDVID change will issue one LDTSTOP and the HT change will be
- * effective too.
- */
- if (needs_reset) {
- printk(BIOS_INFO, "ht reset -\n");
- soft_reset();
- }
- allow_all_aps_stop(bsp_apicid);
-
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
-
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
-}
diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig
deleted file mode 100644
index 60ed865fad..0000000000
--- a/src/mainboard/asus/m2v-mx_se/Kconfig
+++ /dev/null
@@ -1,70 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Cristi Măgherușan <cristi.magherusan@net.utcluj.ro>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-if BOARD_ASUS_M2V_MX_SE
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_AM2
- select DIMM_DDR2
- select QRANK_DIMM_SUPPORT
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_VIA_VT8237R
- select SOUTHBRIDGE_VIA_K8T890
- select SOUTHBRIDGE_VIA_SUBTYPE_K8M890
- select SUPERIO_ITE_IT8712F
- select HAVE_OPTION_TABLE
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_512
- select VGA
- select HAVE_ACPI_RESUME
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default asus/m2v-mx_se
-
-config DCACHE_RAM_BASE
- hex
- default 0xcc000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x4000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MAINBOARD_PART_NUMBER
- string
- default "M2V-MX SE"
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-endif # BOARD_ASUS_M2V_MX_SE
diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig.name b/src/mainboard/asus/m2v-mx_se/Kconfig.name
deleted file mode 100644
index f15d444131..0000000000
--- a/src/mainboard/asus/m2v-mx_se/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_M2V_MX_SE
- bool "M2V-MX SE"
diff --git a/src/mainboard/asus/m2v-mx_se/acpi_tables.c b/src/mainboard/asus/m2v-mx_se/acpi_tables.c
deleted file mode 100644
index 397d310a99..0000000000
--- a/src/mainboard/asus/m2v-mx_se/acpi_tables.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Written by Stefan Reinauer <stepan@openbios.org>.
- * ACPI FADT, FACS, and DSDT table support added by
- *
- * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
- * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/device.h>
-#include <device/pci_ids.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
-#include "northbridge/amd/amdk8/acpi.h"
-#include <cpu/amd/powernow.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-void get_bus_conf(void)
-{
- /* FIXME: implement this. */
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int gsi_base = 0x18;
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- VT8237R_APIC_ID, IO_APIC_ADDR, 0);
-
- /* Write NB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
-
- /* IRQ9 ACPI active low. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* IRQ0 -> APIC IRQ2. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0x0);
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/asus/m2v-mx_se/board_info.txt b/src/mainboard/asus/m2v-mx_se/board_info.txt
deleted file mode 100644
index 00139ad873..0000000000
--- a/src/mainboard/asus/m2v-mx_se/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: desktop
-Board URL: http://www.asus.com/Motherboards/AMD_AM2/M2VMX_SE/
-ROM package: DIP8
-ROM protocol: SPI
-ROM socketed: y
-Flashrom support: y
-Release year: 2007
diff --git a/src/mainboard/asus/m2v-mx_se/cmos.default b/src/mainboard/asus/m2v-mx_se/cmos.default
deleted file mode 100644
index fae766bc88..0000000000
--- a/src/mainboard/asus/m2v-mx_se/cmos.default
+++ /dev/null
@@ -1,11 +0,0 @@
-boot_option = Fallback
-hw_scrubber = Enable
-interleave_chip_selects = Enable
-max_mem_clock = DDR2-400
-multi_core = Enable
-power_on_after_fail = On
-debug_level = Spew
-slow_cpu = off
-nmi = Disable
-videoram_size = 8MB
-iommu = Enable
diff --git a/src/mainboard/asus/m2v-mx_se/cmos.layout b/src/mainboard/asus/m2v-mx_se/cmos.layout
deleted file mode 100644
index 29476ecc33..0000000000
--- a/src/mainboard/asus/m2v-mx_se/cmos.layout
+++ /dev/null
@@ -1,60 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-448 3 e 10 videoram_size
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-# videoram_size: mimics the bits in the ramcontroller.
-10 1 8MB
-10 2 16MB
-10 3 32MB
-10 4 64MB
-10 5 128MB
-10 6 256MB
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/m2v-mx_se/devicetree.cb b/src/mainboard/asus/m2v-mx_se/devicetree.cb
deleted file mode 100644
index 213e3ea9c0..0000000000
--- a/src/mainboard/asus/m2v-mx_se/devicetree.cb
+++ /dev/null
@@ -1,77 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # APIC cluster
- chip cpu/amd/socket_AM2 # CPU
- device lapic 0 on end # APIC
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x1043 0 inherit
- chip northbridge/amd/amdk8 # mc0
- device pci 18.0 on # Northbridge
- # Devices on link 0, link 0 == LDT 0
- chip southbridge/via/vt8237r # Southbridge
- register "ide0_enable" = "1" # Enable IDE channel 0
- register "ide1_enable" = "1" # Enable IDE channel 1
- register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
- register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
- register "fn_ctrl_lo" = "0xc0" # Enable SB functions
- register "fn_ctrl_hi" = "0x1d" # Enable SB functions
- device pci 0.0 on end # HT
- device pci f.1 on end # IDE
- device pci 11.0 on # LPC
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- chip superio/ite/it8712f # Super I/O
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.3 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 on # Environment controller
- io 0x60 = 0x290
- io 0x62 = 0x230
- irq 0x70 = 0x00
- end
- device pnp 2e.5 off end # PS/2 keyboard
- device pnp 2e.6 off end # PS/2 mouse
- device pnp 2e.7 off end # GPIO config
- device pnp 2e.8 off end # Midi port
- device pnp 2e.9 off end # Game port
- device pnp 2e.a off end # IR
- end
- end
- device pci 12.0 on end # VIA LAN
- device pci 13.0 on end # br
- device pci 13.1 on end # br2 need to have it here to discover it
- end
- chip southbridge/via/k8t890 # "Southbridge" K8M890
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/asus/m2v-mx_se/dsdt.asl b/src/mainboard/asus/m2v-mx_se/dsdt.asl
deleted file mode 100644
index 30ce550996..0000000000
--- a/src/mainboard/asus/m2v-mx_se/dsdt.asl
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1)
-{
- #include "northbridge/amd/amdk8/util.asl"
-
- #include <southbridge/via/k8t890/acpi/sleepstates.asl>
-
- /* blink a LED when entering the sleep (any type) */
- Method (_PTS, 1, NotSerialized)
- {
- Store (0x1, \_SB.PCI0.ISA.LEDR)
- }
-
- /* cancel a LED blinking when waking from sleep (any type) */
- Method (_WAK, 1, NotSerialized)
- {
- Store (0x0, \_SB.PCI0.ISA.LEDR)
- /* wake OK */
- Return(Package(0x02){0x00, 0x00})
- }
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_UID, 0x00)
- Name (_BBN, 0x00)
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16,
- 0x0CF8, // Address Range Minimum
- 0x0CF8, // Address Range Maximum
- 0x01, // Address Alignment
- 0x08, // Address Length
- )
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0CF8, // Address Length
- ,, , TypeStatic)
- })
- /* Methods bellow use SSDT to get actual MMIO regs
- The IO ports are from 0xd00, optionally an VGA,
- otherwise the info from MMIO is used.
- */
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- /* PCI Routing Table */
- Name (_PRT, Package () {
- Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x15 }, /* 0xf SATA IRQ 21 */
- Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x14 }, /* 0xf Native IDE IRQ 20 */
- Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x14 }, /* USB routing */
- Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x16 },
- Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
- Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x17 },
- Package (0x04) { 0x0012FFFF, 0x00, 0x00, 0x17 }, /* LAN */
- Package (0x04) { 0x0013FFFF, 0x00, 0x00, 0x14 }, /* PCIe bridge SB */
- Package (0x04) { 0x0013FFFF, 0x02, 0x00, 0x16 }, /* PCIe bridge SB */
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, /* AGP pridge */
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, /* FIXME FIXME */
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, /* PCIE16 bridge IRQ27 */
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, /* PCIE bridge IRQ31 */
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, /* IRQ36 */
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, /* IRQ39 */
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B } /* IRQ43 */
- })
-
- Device (PEGG)
- {
- Name (_ADR, 0x00020000)
- Name (_UID, 0x00)
- Name (_BBN, 0x02)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
- })
- }
-
- Device (PEX0)
- {
- Name (_ADR, 0x00030000)
- Name (_UID, 0x00)
- Name (_BBN, 0x03)
- Name (_PRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
- })
- }
-
- Device (PEX1)
- {
- Name (_ADR, 0x00130000)
- Name (_UID, 0x00)
- Name (_BBN, 0x4)
- Name (_PRT, Package () {
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x11 }, /* PCIE audio */
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x11 },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x11 },
- })
- }
-
- Device (TBRG)
- {
- Name (_ADR, 0x00130001)
- Name (_UID, 0x00)
- Name (_BBN, 0x5)
- Name (_PRT, Package () {
- Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x10 }, /* PCI slot */
- Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 },
- Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x11 }, /* PCI slot */
- Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x10 },
- })
- }
- Device (ISA) {
- Name (_ADR, 0x00110000)
- OperationRegion (PCIC, PCI_Config, 0x0, 0xff)
- Field (PCIC, ByteAcc, NoLock, Preserve)
- {
- Offset (0x94),
- /* two LSB bits are blink rate */
- LEDR, 2,
- }
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 floppy controller */
- Device (FDC0)
- {
- Name (_HID, EisaId ("PNP0700"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () {
- IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
- IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
- IRQNoFlags () {6}
- DMA (Compatibility, NotBusMaster, Transfer8) {2}
- })
- Return (BUF0)
- }
- }
- }
- /* Dummy device to hold auto generated reserved resources */
- Device(MBRS) {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
- External(_CRS) /* Resource Template in SSDT */
- }
- }
- }
-}
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
deleted file mode 100644
index 322f76302f..0000000000
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2006 MSI
- * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
- * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-unsigned int get_sbdn(unsigned bus);
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <halt.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8712f/it8712f.h>
-#include <southbridge/via/vt8237r/vt8237r.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <spd.h>
-#include <northbridge/amd/amdk8/f.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "southbridge/via/k8t890/early_car.c"
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-
-#define SB_VFSMAF 0
-
-static void ldtstop_sb(void)
-{
- printk(BIOS_DEBUG, "toggle LDTSTP#\n");
-
- /* fix errata #181, disable DRAM controller it will get enabled later */
- u8 tmp = pci_read_config8(PCI_DEV(0, 0x18, 2), 0x94);
- tmp |= (( 1 << 14) | (1 << 3));
- pci_write_config8(PCI_DEV(0, 0x18, 2), 0x94, tmp);
-
- u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c);
- reg = reg ^ (1 << 0);
- outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
- reg = inb(VT8237R_ACPI_IO_BASE + 0x15);
- printk(BIOS_DEBUG, "done\n");
-}
-
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-
-void do_soft_reset(void)
-{
- uint8_t tmp;
-
- set_bios_reset();
- printk(BIOS_DEBUG, "soft reset\n");
-
- /* PCI reset */
- tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
- tmp |= 0x01;
- /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
- pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
-
- halt();
-}
-
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
- return (dev >> 15) & 0x1f;
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
- unsigned bsp_apicid = 0;
- int needs_reset = 0;
- struct sys_info *sysinfo = &sysinfo_car;
-
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- ite_kill_watchdog(GPIO_DEV);
- ite_enable_3vsbsw(GPIO_DEV);
- console_init();
- enable_rom_decode();
-
- printk(BIOS_INFO, "now booting...\n");
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- /* Halt if there was a built in self test failure. */
- report_bist_failure(bist);
- setup_default_resource_map();
- setup_coherent_ht_domain();
- wait_all_core0_started();
-
- printk(BIOS_INFO, "now booting... All core 0 started\n");
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched. */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
- init_timer();
- ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
-
- needs_reset = optimize_link_coherent_ht();
- printk(BIOS_DEBUG, "%02x", needs_reset);
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- printk(BIOS_DEBUG, "%02x", needs_reset);
- needs_reset |= k8t890_early_setup_ht();
- printk(BIOS_DEBUG, "%02x", needs_reset);
-
- vt8237_early_network_init(NULL);
- vt8237_early_spi_init();
-
- if (needs_reset) {
- printk(BIOS_DEBUG, "ht reset -\n");
- soft_reset();
- printk(BIOS_DEBUG, "FAILED!\n");
- }
-
- /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
- /* allow LDT STOP asserts */
- vt8237_sb_enable_fid_vid();
-
- enable_fid_change();
- printk(BIOS_DEBUG, "after enable_fid_change\n");
-
- init_fidvid_bsp(bsp_apicid);
-
- /* Stop the APs so we can start them later in init. */
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl now. */
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
- enable_smbus();
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}
diff --git a/src/mainboard/asus/m2v/Kconfig b/src/mainboard/asus/m2v/Kconfig
deleted file mode 100644
index 26bfeef26f..0000000000
--- a/src/mainboard/asus/m2v/Kconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-if BOARD_ASUS_M2V
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_AMD_SOCKET_AM2
- select DIMM_DDR2
- select QRANK_DIMM_SUPPORT
- select K8_HT_FREQ_1G_SUPPORT
- select NORTHBRIDGE_AMD_AMDK8
- select SOUTHBRIDGE_VIA_VT8237R
- select SOUTHBRIDGE_VIA_K8T890
- select SOUTHBRIDGE_VIA_SUBTYPE_K8T890
- select SUPERIO_ITE_IT8712F
- select HAVE_OPTION_TABLE
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_512
- select HAVE_ACPI_RESUME
- select HAVE_PIRQ_TABLE
- select PIRQ_ROUTE
- select HAVE_MP_TABLE
- select SET_FIDVID
-
-config MAINBOARD_DIR
- string
- default asus/m2v
-
-config DCACHE_RAM_BASE
- hex
- default 0xcc000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x4000
-
-config APIC_ID_OFFSET
- hex
- default 0x10
-
-config MAINBOARD_PART_NUMBER
- string
- default "M2V"
-
-config HW_MEM_HOLE_SIZEK
- hex
- default 0x0
-
-config MAX_CPUS
- int
- default 2
-
-config MAX_PHYSICAL_CPUS
- int
- default 1
-
-config HT_CHAIN_UNITID_BASE
- hex
- default 0x0
-
-config HT_CHAIN_END_UNITID_BASE
- hex
- default 0x20
-
-config IRQ_SLOT_COUNT
- int
- default 14
-
-endif # BOARD_ASUS_M2V
diff --git a/src/mainboard/asus/m2v/Kconfig.name b/src/mainboard/asus/m2v/Kconfig.name
deleted file mode 100644
index c0fc2f31a3..0000000000
--- a/src/mainboard/asus/m2v/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_ASUS_M2V
- bool "M2V"
diff --git a/src/mainboard/asus/m2v/acpi_tables.c b/src/mainboard/asus/m2v/acpi_tables.c
deleted file mode 100644
index fce0fb6db2..0000000000
--- a/src/mainboard/asus/m2v/acpi_tables.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Written by Stefan Reinauer <stepan@openbios.org>.
- * ACPI FADT, FACS, and DSDT table support added by
- *
- * Copyright (C) 2004 Stefan Reinauer <stepan@openbios.org>
- * Copyright (C) 2005 Nick Barker <nick.barker9@btinternet.com>
- * Copyright (C) 2007, 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
-#include "northbridge/amd/amdk8/acpi.h"
-#include <cpu/amd/powernow.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-void get_bus_conf(void)
-{
- /* FIXME: implement this. */
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int gsi_base = 0x18;
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapics(current);
-
- /* Write SB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- VT8237R_APIC_ID, IO_APIC_ADDR, 0);
-
- /* Write NB IOAPIC. */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
- K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base);
-
- /* IRQ9 ACPI active low. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
-
- /* IRQ0 -> APIC IRQ2. */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0x0);
-
- /* Create all subtables for processors. */
- current = acpi_create_madt_lapic_nmis(current,
- MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
-
- return current;
-}
diff --git a/src/mainboard/asus/m2v/board_info.txt b/src/mainboard/asus/m2v/board_info.txt
deleted file mode 100644
index 1abcb5b361..0000000000
--- a/src/mainboard/asus/m2v/board_info.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Category: desktop
-Board URL: http://www.asus.com/Motherboards/AMD_AM2/M2V/
-ROM package: PLCC
-ROM protocol: LPC
-ROM socketed: y
-Flashrom support: y
-Release year: 2007
diff --git a/src/mainboard/asus/m2v/cmos.layout b/src/mainboard/asus/m2v/cmos.layout
deleted file mode 100644
index aae7ceb075..0000000000
--- a/src/mainboard/asus/m2v/cmos.layout
+++ /dev/null
@@ -1,52 +0,0 @@
-entries
-
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-388 4 h 0 reboot_counter
-#392 3 r 0 unused
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 multi_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-456 1 e 1 ECC_memory
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 amd_reserved
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-6 5 Notice
-6 6 Info
-6 7 Debug
-6 8 Spew
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/asus/m2v/devicetree.cb b/src/mainboard/asus/m2v/devicetree.cb
deleted file mode 100644
index 61d94bad3f..0000000000
--- a/src/mainboard/asus/m2v/devicetree.cb
+++ /dev/null
@@ -1,75 +0,0 @@
-chip northbridge/amd/amdk8/root_complex # Root complex
- device cpu_cluster 0 on # APIC cluster
- chip cpu/amd/socket_AM2 # CPU
- device lapic 0 on end # APIC
- end
- end
- device domain 0 on # PCI domain
- subsystemid 0x1043 0 inherit
- chip northbridge/amd/amdk8 # mc0
- device pci 18.0 on # Northbridge
- # Devices on link 0, link 0 == LDT 0
- chip southbridge/via/vt8237r # Southbridge
- register "ide0_enable" = "1" # Enable IDE channel 0
- register "ide1_enable" = "1" # Enable IDE channel 1
- register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
- register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
- register "fn_ctrl_lo" = "0xc0" # Enable SB functions
- register "fn_ctrl_hi" = "0x0d" # Enable SB functions
- device pci 0.0 on end # HT
- device pci f.1 on end # IDE
- device pci 11.0 on # LPC
- chip drivers/generic/generic # DIMM 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic # DIMM 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic # DIMM 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic # DIMM 0-1-1
- device i2c 53 on end
- end
- chip superio/ite/it8712f # Super I/O
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.2 off end # Com2 (N/A on this board)
- device pnp 2e.3 on # Lpt1
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 3
- end
- device pnp 2e.4 on # Environment controller
- io 0x60 = 0xd00
- io 0x62 = 0xc00
- irq 0x70 = 0x00
- end
- device pnp 2e.5 off end # PS/2 keyboard
- device pnp 2e.6 off end # PS/2 mouse
- device pnp 2e.7 off end # GPIO config
- device pnp 2e.8 off end # Midi port
- device pnp 2e.9 off end # Game port
- device pnp 2e.a off end # IR
- end
- end
- device pci 12.0 off end # VIA LAN (off, other chip used)
- device pci 13.0 on end # br
- device pci 13.1 on end # br2, need to have it here to discover it
- end
- chip southbridge/via/k8t890 # "Southbridge" K8T890
- end
- end
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- end
-end
diff --git a/src/mainboard/asus/m2v/dsdt.asl b/src/mainboard/asus/m2v/dsdt.asl
deleted file mode 100644
index 760d5e214c..0000000000
--- a/src/mainboard/asus/m2v/dsdt.asl
+++ /dev/null
@@ -1,545 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com>
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * ISA portions taken from QEMU acpi-dsdt.dsl.
- */
-
-#define LNKA INTA
-#define LNKB INTB
-#define LNKC INTC
-#define LNKD INTD
-
-/*
- * For simplicity map LNK[E-H] to LNK[A-D].
- * This also means we are 82C596 compatible.
- * Needs 0:11.0 0x46[4] set to 0.
- */
-#define LNKE INTA
-#define LNKF INTB
-#define LNKG INTC
-#define LNKH INTD
-
-DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
-{
- Name(APIC, 0) // 0=>8259, 1=>IOAPIC
-
- /* The _PIC method is called by the OS to choose between interrupt
- * routing via the i8259 interrupt controller or the APIC.
- *
- * _PIC is called with a parameter of 0 for i8259 configuration and
- * with a parameter of 1 for Local Apic/IOAPIC configuration.
- */
-
- Method(_PIC, 1)
- {
- // Remember the OS' IRQ routing choice.
- Store(Arg0, APIC)
- }
-
- /* _PR CPU0 is dynamically supplied by SSDT */
-
- #include <southbridge/via/k8t890/acpi/sleepstates.asl>
-
- /* Root of the bus hierarchy */
- Scope (\_SB)
- {
- /* Top PCI device */
- Device (PCI0)
- {
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00180000)
- Name (_BBN, 0x00)
-
- Name (APRT, Package() {
- /* AGP? */
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 },
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x13 },
- /* PCIe graphics bridge */
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B },
- /* PCIe bridge */
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F },
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 },
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 },
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B },
- /* SATA */
- Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x15 },
- /* IDE */
- Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x15 },
- /* USB */
- Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x14 },
- Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x16 },
- Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 },
- Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x17 },
- /* PCI bridge */
- Package (0x04) { 0x0013FFFF, 0x00, 0x00, 0x14 },
- Package (0x04) { 0x0013FFFF, 0x01, 0x00, 0x14 },
- Package (0x04) { 0x0013FFFF, 0x02, 0x00, 0x14 },
- Package (0x04) { 0x0013FFFF, 0x03, 0x00, 0x14 },
- })
- Name (PPRT, Package() {
- /* ?? */
- Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x01, LNKB, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x02, LNKC, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x03, LNKD, 0x00 },
- /* PCIe graphics bridge */
- Package (0x04) { 0x0002FFFF, 0x00, LNKH, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x01, LNKH, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x02, LNKH, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x03, LNKH, 0x00 },
- /* PCIe bridge */
- Package (0x04) { 0x0003FFFF, 0x00, LNKH, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x01, LNKH, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x02, LNKH, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x03, LNKH, 0x00 },
- /* SATA */
- Package (0x04) { 0x000FFFFF, 0x01, LNKB, 0x00 },
- /* USB */
- Package (0x04) { 0x0010FFFF, 0x00, LNKA, 0x00 },
- Package (0x04) { 0x0010FFFF, 0x01, LNKB, 0x00 },
- Package (0x04) { 0x0010FFFF, 0x02, LNKC, 0x00 },
- Package (0x04) { 0x0010FFFF, 0x03, LNKD, 0x00 },
- /* PCI bridge */
- Package (0x04) { 0x0013FFFF, 0x00, LNKD, 0x00 },
- Package (0x04) { 0x0013FFFF, 0x01, LNKD, 0x00 },
- Package (0x04) { 0x0013FFFF, 0x02, LNKD, 0x00 },
- Package (0x04) { 0x0013FFFF, 0x03, LNKD, 0x00 },
- })
-
- /* PCI Routing Table */
- Method (_PRT, 0, NotSerialized)
- {
- If (APIC)
- {
- Return (APRT)
- }
- Return (PPRT)
- }
-
- Device (PEGG)
- {
- Name (_ADR, 0x00020000)
- Name (APRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B },
- })
- Name (PPRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (APIC)
- {
- Return (APRT)
- }
- Return (PPRT)
- }
- }
-
- Device (PEX0)
- {
- Name (_ADR, 0x00030000)
- Name (APRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F },
- })
- Name (PPRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (APIC)
- {
- Return (APRT)
- }
- Return (PPRT)
- }
- }
-
- Device (PEX1)
- {
- Name (_ADR, 0x00030001)
- Name (APRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 },
- })
- Name (PPRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (APIC)
- {
- Return (APRT)
- }
- Return (PPRT)
- }
- }
-
- Device (PEX2)
- {
- Name (_ADR, 0x00030002)
- Name (APRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 },
- })
- Name (PPRT, Package () {
- Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 },
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (APIC)
- {
- Return (APRT)
- }
- Return (PPRT)
- }
- }
-
- Device (PCI6)
- {
- Name (_ADR, 0x00130000)
- Name (APRT, Package () {
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x11 }, /* IRQ17 */
- })
- Name (PPRT, Package () {
- Package (0x04) { 0x0001FFFF, 0x00, LNKB, 0x00 },
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (APIC)
- {
- Return (APRT)
- }
- Return (PPRT)
- }
- }
-
- Device (PCI7)
- {
- Name (_ADR, 0x00130001)
- Name (APRT, Package () {
- /* PCI slot 1 */
- Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x10 },
- Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 },
-
- /* PCI slot 2 */
- Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x11 },
- Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x10 },
-
- /* PCI slot 3 */
- Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x12 },
- Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x13 },
- Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x10 },
- Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x11 },
-
- /* PCI slot 4 */
- Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x13 },
- Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x10 },
- Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x11 },
- Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x12 },
- })
- Name (PPRT, Package () {
- /* PCI slot 1 */
- Package (0x04) { 0x0006FFFF, 0x00, LNKA, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x01, LNKB, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x02, LNKC, 0x00 },
- Package (0x04) { 0x0006FFFF, 0x03, LNKD, 0x00 },
-
- /* PCI slot 2 */
- Package (0x04) { 0x0007FFFF, 0x00, LNKB, 0x00 },
- Package (0x04) { 0x0007FFFF, 0x01, LNKC, 0x00 },
- Package (0x04) { 0x0007FFFF, 0x02, LNKD, 0x00 },
- Package (0x04) { 0x0007FFFF, 0x03, LNKA, 0x00 },
-
- /* PCI slot 3 */
- Package (0x04) { 0x0008FFFF, 0x00, LNKC, 0x00 },
- Package (0x04) { 0x0008FFFF, 0x01, LNKD, 0x00 },
- Package (0x04) { 0x0008FFFF, 0x02, LNKA, 0x00 },
- Package (0x04) { 0x0008FFFF, 0x03, LNKB, 0x00 },
-
- /* PCI slot 4 */
- Package (0x04) { 0x0009FFFF, 0x00, LNKD, 0x00 },
- Package (0x04) { 0x0009FFFF, 0x01, LNKA, 0x00 },
- Package (0x04) { 0x0009FFFF, 0x02, LNKB, 0x00 },
- Package (0x04) { 0x0009FFFF, 0x03, LNKC, 0x00 },
- })
-
- Method (_PRT, 0, NotSerialized)
- {
- If (APIC)
- {
- Return (APRT)
- }
- Return (PPRT)
- }
- }
-
- Device (SBRG) { /* southbridge */
- Name (_ADR, 0x00110000)
- OperationRegion (PCIC, PCI_Config, 0x0, 0x100)
-
- /* PS/2 keyboard (seems to be important for WinXP install) */
- Device (KBD)
- {
- Name (_HID, EisaId ("PNP0303"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, Serialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- Return (TMP)
- }
- }
-
- /* PS/2 mouse */
- Device (MOU)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, Serialized)
- {
- Name (TMP, ResourceTemplate () {
- IRQNoFlags () {12}
- })
- Return (TMP)
- }
- }
-
- /* Parallel port */
- Device (LPT0)
- {
- Name (_HID, EisaId ("PNP0401"))
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0f)
- }
- Method (_CRS, 0, Serialized)
- {
- Name (TMP, ResourceTemplate () {
- IO (Decode16, 0x0378, 0x0378, 0x01, 0x08)
- IO (Decode16, 0x0778, 0x0778, 0x01, 0x08)
- IRQNoFlags () {7}
- DMA (Compatibility, NotBusMaster, Transfer8) {3}
- })
- Return (TMP)
- }
- }
- }
-
- Device(MBRS) {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
-
- External(_CRS) /* Resource Template in SSDT */
- }
-
- External(TOM1) /* top of memory below 4GB */
-
- Method(_CRS, 0, Serialized) {
- Name(TMP, ResourceTemplate() {
- WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, // Granularity
- 0x0000, // Range Minimum
- 0x00FF, // Range Maximum
- 0x0000, // Translation Offset
- 0x0100, // Length
- ,,
- )
- IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0000, /* range minimum */
- 0x0CF7, /* range maximum */
- 0x0000, /* translation */
- 0x0CF8 /* length */
- )
-
- WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, /* address granularity */
- 0x0D00, /* range minimum */
- 0xFFFF, /* range maximum */
- 0x0000, /* translation */
- 0xF300 /* length */
- )
-
- /* memory space for PCI BARs below 4GB */
- Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
- })
- CreateDWordField(TMP, MMIO._BAS, MM1B)
- CreateDWordField(TMP, MMIO._LEN, MM1L)
- /*
- * Declare memory between TOM1 and 4GB as available
- * for PCI MMIO.
- *
- * Use ShiftLeft to avoid 64bit constant (for XP).
- * This will work even if the OS does 32bit arithmetic, as
- * 32bit (0x00000000 - TOM1) will wrap and give the same
- * result as 64bit (0x100000000 - TOM1).
- */
- Store(TOM1, MM1B)
- ShiftLeft(0x10000000, 4, Local0)
- Subtract(Local0, TOM1, Local0)
- Store(Local0, MM1L)
-
- Return(TMP)
- }
- }
-
- Field (PCI0.SBRG.PCIC, ByteAcc, NoLock, Preserve)
- {
- Offset (0x55),
- /*
- * Offset 0x55:
- * 3-0: reserved
- * 7-4: PCI INTA# routing
- * Offset 0x56:
- * 3-0: PCI INTB# routing
- * 7-4: PCI INTC# routing
- * Offset 0x57:
- * 3-0: reserved
- * 7-4: PCI INTD# routing
- *
- * Valid values for routing link:
- * 0: disabled
- * 2,8,13: reserved
- * 1,3-7,9-12,14,15: corresponding irq
- */
- , 4,
- PINA, 4,
- PINB, 4,
- PINC, 4,
- , 4,
- PIND, 4,
- }
-
- Name(IRQB, ResourceTemplate(){
- IRQ(Level,ActiveLow,Shared){15}
- })
-
- Name(IRQP, ResourceTemplate(){
- IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 6, 7, 10, 11, 12}
- })
-
- /* adapted from ma78gm/dsdt.asl */
-#define PCI_INTX_DEV(intx, pinx, uid) \
- Device(intx) { \
- Name(_HID, EISAID("PNP0C0F")) \
- Name(_UID, uid) \
- \
- Method(_STA, 0) { \
- if (pinx) { \
- Return(0x0B) \
- } \
- Return(0x09) \
- } \
- \
- Method(_DIS ,0) { \
- Store(0, pinx) \
- } \
- \
- Method(_PRS ,0) { \
- Return(IRQP) \
- } \
- \
- Method(_CRS ,0) { \
- CreateWordField(IRQB, 1, IRQN) \
- ShiftLeft(1, pinx, IRQN) \
- Return(IRQB) \
- } \
- \
- Method(_SRS, 1) { \
- CreateWordField(ARG0, 1, IRQM) \
- \
- /* Use lowest available IRQ */ \
- FindSetRightBit(IRQM, Local0) \
- if (Local0) { \
- Decrement(Local0) \
- } \
- Store(Local0, pinx) \
- } \
- } \
-
-PCI_INTX_DEV(INTA, PINA, 1)
-PCI_INTX_DEV(INTB, PINB, 2)
-PCI_INTX_DEV(INTC, PINC, 3)
-PCI_INTX_DEV(INTD, PIND, 4)
- }
-
- Field (_SB.PCI0.SBRG.PCIC, ByteAcc, NoLock, Preserve)
- {
- Offset (0x94),
- /* two LSB bits are blink rate */
- LEDR, 2,
- }
-
- Method (_PTS, 1, NotSerialized)
- {
- /* blink power led while suspended */
- Store (0x1, LEDR)
- }
-
- Method (_WAK, 1, NotSerialized)
- {
- /* stop power led blinking */
- Store (0x0, LEDR)
- /* wake OK */
- Return(Package(0x02){0x00, 0x00})
- }
-}
diff --git a/src/mainboard/asus/m2v/irq_tables.c b/src/mainboard/asus/m2v/irq_tables.c
deleted file mode 100644
index 18bebf545e..0000000000
--- a/src/mainboard/asus/m2v/irq_tables.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * IRQ Routing Table
- *
- * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
- */
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-#include <device/pci_ids.h>
-
-/* Free irqs are 3, 5, 10 and 11 */
-#define IRQBM ((1 << 3)|(1 << 5)|(1 << 10)|(1 << 11))
-
-#define LNKA 1
-#define LNKB 2
-#define LNKC 3
-#define LNKD 4
-
-/*
- * For simplicity map LNK[E-H] to LNK[A-D].
- * This also means we are 82C596 compatible.
- * Needs 0:11.0 0x46[4] set to 0.
- */
-#define LNKE 1
-#define LNKF 2
-#define LNKG 3
-#define LNKH 4
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
- 0, /* Where the interrupt router lies (bus) */
- (0x11 << 3)|0, /* Where the interrupt router lies (dev) */
- 0, /* IRQs devoted exclusively to PCI usage */
- PCI_VENDOR_ID_VIA, /* Compatible Vendor (VIA) */
- PCI_DEVICE_ID_VIA_82C596, /* Compatible Device (82C596) */
- 0, /* Miniport data */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x5f, /* u8 checksum, this has to be set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
- {
- /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- /* peg bridge */
- {0x00, (0x02 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0},
- /* pcie bridge */
- {0x00, (0x03 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0},
- /* sata/ide */
- {0x00, (0x0f << 3) | 0x0, {{0x00, 0x0000}, {LNKB, IRQBM}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
- /* usb */
- {0x00, (0x10 << 3) | 0x0, {{LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}}, 0x0, 0x0},
- /* agp bus? */
- {0x01, (0x00 << 3) | 0x0, {{LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}}, 0x0, 0x0},
- /* pcie graphics */
- {0x02, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x6, 0x0},
- /* onboard pcie atl1 ethernet */
- {0x03, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0},
- /* pcie slot */
- {0x04, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x5, 0x0},
- /* onboard marvell mv6121 sata */
- {0x05, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0},
- /* Azalia HDAC */
- {0x06, (0x01 << 3) | 0x0, {{LNKB, IRQBM}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
- /* PCI slots */
- {0x07, (0x06 << 3) | 0x0, {{LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}}, 0x1, 0x0},
- {0x07, (0x07 << 3) | 0x0, {{LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}, {LNKA, IRQBM}}, 0x2, 0x0},
- {0x07, (0x08 << 3) | 0x0, {{LNKC, IRQBM}, {LNKD, IRQBM}, {LNKA, IRQBM}, {LNKB, IRQBM}}, 0x3, 0x0},
- {0x07, (0x09 << 3) | 0x0, {{LNKD, IRQBM}, {LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}}, 0x4, 0x0},
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/asus/m2v/mainboard.c b/src/mainboard/asus/m2v/mainboard.c
deleted file mode 100644
index e16faebfae..0000000000
--- a/src/mainboard/asus/m2v/mainboard.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <console/console.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-
-u32 vt8237_ide_80pin_detect(struct device *dev)
-{
- struct device *lpc_dev;
- u16 acpi_io_base;
- u32 gpio_in;
- u32 res;
-
- lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237A_LPC, 0);
- if (!lpc_dev)
- return 0;
-
- acpi_io_base = pci_read_config16(lpc_dev, 0x88) & ~1;
- if (!acpi_io_base)
- return 0;
-
- gpio_in = inl(acpi_io_base + 0x48);
- /* bit 9 for primary port, clear if unconnected or 80-pin cable */
- res = gpio_in & (1 << 9) ? 0 : VT8237R_IDE0_80PIN_CABLE;
- /* bit 4 for secondary port, clear if unconnected or 80-pin cable */
- res |= gpio_in & (1 << 4) ? 0 : VT8237R_IDE1_80PIN_CABLE;
-
- printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "primary",
- res & VT8237R_IDE0_80PIN_CABLE ? 80 : 40);
- printk(BIOS_INFO, "Cable on %s PATA port: %d pin\n", "secondary",
- res & VT8237R_IDE1_80PIN_CABLE ? 80 : 40);
-
- return res;
-}
diff --git a/src/mainboard/asus/m2v/mptable.c b/src/mainboard/asus/m2v/mptable.c
deleted file mode 100644
index 8de77ccdb5..0000000000
--- a/src/mainboard/asus/m2v/mptable.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <stdint.h>
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "southbridge/via/vt8237r/vt8237r.h"
-#include "southbridge/via/k8t890/k8t890.h"
-
-static void smp_write_intsrc_pci(struct mp_config_table *mc,
- unsigned char srcbus, unsigned char srcbusirq,
- unsigned char dstapic, unsigned char dstirq)
-{
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,
- srcbus, srcbusirq, dstapic, dstirq);
-}
-
-static void *smp_write_config_table(void *v)
-{
- struct mp_config_table *mc;
- int bus_isa;
-
- mc = (void*)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
- mptable_init(mc, LOCAL_APIC_ADDR);
-
- smp_write_processors(mc);
- mptable_write_buses(mc, NULL, &bus_isa);
-
- /* I/O APICs: APIC ID Version State Address */
- smp_write_ioapic(mc, VT8237R_APIC_ID, 0x3, VIO_APIC_VADDR);
- smp_write_ioapic(mc, K8T890_APIC_ID, 0x3, (void*)K8T890_APIC_BASE);
-
- mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
-
- /* agp? bridge */
- smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 0, VT8237R_APIC_ID, 0x10);
- smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 1, VT8237R_APIC_ID, 0x11);
- smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 2, VT8237R_APIC_ID, 0x12);
- smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 3, VT8237R_APIC_ID, 0x13);
-
- /* peg bridge */
- smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3);
- smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3);
- smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3);
- smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3);
-
- /* pex bridge */
- smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7);
- smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb);
- smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf);
- smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13);
-
- /* SATA / IDE */
- smp_write_intsrc_pci(mc, 0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x15);
-
- /* USB */
- smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x14);
- smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x16);
- smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15);
- smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 3, VT8237R_APIC_ID, 0x17);
-
- /* PCIE graphics */
- smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0);
- smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1);
- smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2);
- smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3);
-
- /* onboard PCIE atl1 ethernet */
- smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4);
- smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5);
- smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6);
- smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7);
-
- /* PCIE slot */
- smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8);
- smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9);
- smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa);
- smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb);
-
- /* onboard marvell mv6121 sata */
- smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc);
- smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd);
- smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe);
- smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf);
-
- /* azalia HDCA */
- smp_write_intsrc_pci(mc, 6, (0x01 << 2) | 0, VT8237R_APIC_ID, 0x11);
-
- /* pci slot 1 */
- smp_write_intsrc_pci(mc, 7, (6 << 2) | 0, VT8237R_APIC_ID, 0x10);
- smp_write_intsrc_pci(mc, 7, (6 << 2) | 1, VT8237R_APIC_ID, 0x11);
- smp_write_intsrc_pci(mc, 7, (6 << 2) | 2, VT8237R_APIC_ID, 0x12);
- smp_write_intsrc_pci(mc, 7, (6 << 2) | 3, VT8237R_APIC_ID, 0x13);
-
- /* pci slot 2 */
- smp_write_intsrc_pci(mc, 7, (7 << 2) | 0, VT8237R_APIC_ID, 0x11);
- smp_write_intsrc_pci(mc, 7, (7 << 2) | 1, VT8237R_APIC_ID, 0x12);
- smp_write_intsrc_pci(mc, 7, (7 << 2) | 2, VT8237R_APIC_ID, 0x13);
- smp_write_intsrc_pci(mc, 7, (7 << 2) | 3, VT8237R_APIC_ID, 0x10);
-
- /* pci slot 3 */
- smp_write_intsrc_pci(mc, 7, (8 << 2) | 0, VT8237R_APIC_ID, 0x12);
- smp_write_intsrc_pci(mc, 7, (8 << 2) | 1, VT8237R_APIC_ID, 0x13);
- smp_write_intsrc_pci(mc, 7, (8 << 2) | 2, VT8237R_APIC_ID, 0x10);
- smp_write_intsrc_pci(mc, 7, (8 << 2) | 3, VT8237R_APIC_ID, 0x11);
-
- /* pci slot 4 */
- smp_write_intsrc_pci(mc, 7, (9 << 2) | 0, VT8237R_APIC_ID, 0x13);
- smp_write_intsrc_pci(mc, 7, (9 << 2) | 1, VT8237R_APIC_ID, 0x10);
- smp_write_intsrc_pci(mc, 7, (9 << 2) | 2, VT8237R_APIC_ID, 0x11);
- smp_write_intsrc_pci(mc, 7, (9 << 2) | 3, VT8237R_APIC_ID, 0x12);
-
- /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- mptable_lintsrc(mc, 0);
- /* There is no extension information... */
-
- /* Compute the checksums. */
- return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr, 0);
- return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
deleted file mode 100644
index d49f231f75..0000000000
--- a/src/mainboard/asus/m2v/romstage.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 AMD
- * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
- * Copyright (C) 2006 MSI
- * (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
- * Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-unsigned int get_sbdn(unsigned bus);
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/x86/lapic.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <cpu/amd/model_fxx_rev.h>
-#include <halt.h>
-#include <northbridge/amd/amdk8/raminit.h>
-#include <delay.h>
-
-#include <superio/ite/common/ite.h>
-#include <superio/ite/it8712f/it8712f.h>
-#include <southbridge/via/vt8237r/vt8237r.h>
-#include <cpu/amd/car.h>
-#include <cpu/x86/bist.h>
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-#include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
-#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-
-#define IT8712F_GPIO_BASE 0x0a20
-
-void memreset(int controllers, const struct mem_controller *ctrl) { }
-void activate_spd_rom(const struct mem_controller *ctrl) { }
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "southbridge/via/k8t890/early_car.c"
-#include <northbridge/amd/amdk8/amdk8.h>
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "lib/generic_sdram.c"
-#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/model_fxx/init_cpus.c"
-#include "cpu/amd/model_fxx/fidvid.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-
-void do_soft_reset(void)
-{
- uint8_t tmp;
-
- set_bios_reset();
- printk(BIOS_DEBUG, "soft reset\n");
-
- /* PCI reset */
- tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
- tmp |= 0x01;
- /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
- pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
-
- halt();
-}
-
-unsigned int get_sbdn(unsigned bus)
-{
- pci_devfn_t dev;
-
- dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
- return (dev >> 15) & 0x1f;
-}
-
-struct gpio_init_val {
- u8 addr;
- u8 val;
-};
-
-static const struct gpio_init_val gpio_init_data[] = {
- /* multi-function pin selection */
- { 0x25, 0x00 },
- { 0x28, 0x00 }, /* gp46 is infrared receive input */
- { 0x29, 0x40 }, /* reserved value?!? */
- { 0x2a, 0x00 },
- { 0x2c, 0x1d }, /* pin91 is VIN7 instead of PCIRSTIN# */
- /* gpio i/o port base */
- { 0x62, IT8712F_GPIO_BASE >> 8 },
- { 0x63, IT8712F_GPIO_BASE & 0xff },
- /* 0xb8 - 0xbc: gpio pull-up enable */
- { 0xb8, 0x00 },
- /* 0xc0 - 0xc4: gpio alternate function select */
- { 0xc0, 0x00 },
- { 0xc3, 0x00 },
- { 0xc4, 0xc0 },
- /* 0xc8 - 0xcc: gpio output enable */
- { 0xc8, 0x00 },
- { 0xcb, 0x00 },
- { 0xcc, 0xc0 },
- /* end of list */
- { 0, 0 },
-};
-
-static void m2v_it8712f_gpio_init(void)
-{
- const struct gpio_init_val *giv;
-
- printk(BIOS_SPEW, "it8712f gpio init...\n");
-
- /*
- * it8712f gpio config
- *
- * Most importantly this switches pin 91 from
- * PCIRSTIN# to VIN7.
- * Note that only PCIRST3# and PCIRST5# are affected
- * by PCIRSTIN#, the PCIRST1#, PCIRST2#, PCIRST4# are always
- * direct buffers of #LRESET (low pin count bus reset).
- * If this is not done All PCIRST are in reset state and the
- * pcie slots don't initialize.
- *
- * pci reset handling:
- * pin 91: VIN7 (alternate PCIRSTIN#)
- * pin 48: PCIRST5# / gpio port 5 bit 0
- * pin 84: PCIRST4# / gpio port 1 bit 0
- * pin 31: PCIRST1# / gpio port 1 bit 4
- * pin 33: PCIRST2# / gpio port 1 bit 2
- * pin 34: PCIRST3# / gpio port 1 bit 1
- *
- * PCIRST[0-5]# are connected as follows:
- * pcirst1# -> pci bus
- * pcirst2# -> ide bus
- * pcirst3# -> pcie devices
- * pcirst4# -> pcie graphics
- * pcirst5# -> maybe n/c (untested)
- *
- * For software control of PCIRST[1-5]#:
- * 0x2a = 0x17 (deselect pcirst# hardwiring, enable 0x25 control)
- * 0x25 = 0x17 (select gpio function)
- * 0xc0 = 0x17, 0xc8 = 0x17 gpio port 1 select & output enable
- * 0xc4 = 0xc1, 0xcc = 0xc1 gpio port 5 select & output enable
- */
- giv = gpio_init_data;
- while (giv->addr) {
- printk(BIOS_SPEW, "it8712f gpio: %02x=%02x\n",
- giv->addr, giv->val);
- ite_reg_write(IT8712F_GPIO, giv->addr, giv->val);
- giv++;
- }
-
- printk(BIOS_INFO, "it8712f gpio: Setting DDR2 voltage to 1.80V\n");
- /*
- * upper two bits of gpio_base+4 control ddr2 voltage:
- * 11: 1.80V
- * 01: 1.85V
- * 10: 1.90V
- * 00: 1.95V
- *
- * The lower six bits are inputs and normally read back as 1
- * (except bit 2, which seems rather random).
- */
- outb(0xff, IT8712F_GPIO_BASE+4);
-}
-
-static void m2v_bus_init(void)
-{
- pci_devfn_t dev;
-
- printk(BIOS_SPEW, "m2v_bus_init\n");
-
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_K8T890CF_0), 0);
- pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
-
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_K8T890CF_5), 0);
- /*
- * bit | meaning
- * 6 | 0: hide scratch register function 0:0.6 (we don't use it)
- * 5 | 1: enable pcie bridge 0:2.0
- * 4 | 0: hide pcie bridge 0:3.3 (not connected)
- * 3 | 1: enable pcie bridge 0:3.2
- * 2 | 1: enable pcie bridge 0:3.1
- * 1 | 1: enable pcie bridge 0:3.0
- */
- pci_write_config8(dev, 0xf0, 0x2e);
-}
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
- };
- unsigned bsp_apicid = 0;
- int needs_reset = 0;
- struct sys_info *sysinfo = &sysinfo_car;
-
- ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24);
- ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- ite_kill_watchdog(GPIO_DEV);
- console_init();
- enable_rom_decode();
- m2v_bus_init();
- m2v_it8712f_gpio_init();
- ite_enable_3vsbsw(GPIO_DEV);
-
- printk(BIOS_INFO, "now booting...\n");
-
- if (bist == 0)
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-
- /* Halt if there was a built in self test failure. */
- report_bist_failure(bist);
- setup_default_resource_map();
- setup_coherent_ht_domain();
- wait_all_core0_started();
-
- printk(BIOS_INFO, "now booting... All core 0 started\n");
-
-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
- /* It is said that we should start core1 after all core0 launched. */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
- init_timer();
- ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
-
- needs_reset = optimize_link_coherent_ht();
- printk(BIOS_DEBUG, "%02x", needs_reset);
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
- printk(BIOS_DEBUG, "%02x", needs_reset);
- needs_reset |= k8t890_early_setup_ht();
- printk(BIOS_DEBUG, "%02x", needs_reset);
-
- if (needs_reset) {
- printk(BIOS_DEBUG, "ht reset -\n");
- soft_reset();
- printk(BIOS_DEBUG, "FAILED!\n");
- }
-
- /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
- /* allow LDT STOP asserts */
- vt8237_sb_enable_fid_vid();
-
- enable_fid_change();
- printk(BIOS_DEBUG, "after enable_fid_change\n");
-
- init_fidvid_bsp(bsp_apicid);
-
- /* Stop the APs so we can start them later in init. */
- allow_all_aps_stop(bsp_apicid);
-
- /* It's the time to set ctrl now. */
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
- enable_smbus();
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-}