summaryrefslogtreecommitdiff
path: root/src/mainboard/asus
diff options
context:
space:
mode:
authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-09-21 12:32:43 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-09-26 08:36:05 +0000
commite52738b42889a8bf6b96fe86b87fbdd73947b367 (patch)
treeab3ddcc914b9ab69fdb793ba42e30480d9a8824f /src/mainboard/asus
parente1dced4561ed3b7bff98984c1d51b8e84f004b47 (diff)
downloadcoreboot-e52738b42889a8bf6b96fe86b87fbdd73947b367.tar.xz
AGESA binaryPI boards: Fix some whitespace
Change-Id: I150d4a71536137a725f43d900d483e7e35592bb3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/mainboard/asus')
-rw-r--r--src/mainboard/asus/f2a85-m/OemCustomize.c44
1 files changed, 22 insertions, 22 deletions
diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c
index 316a110991..5ecba8ee6a 100644
--- a/src/mainboard/asus/f2a85-m/OemCustomize.c
+++ b/src/mainboard/asus/f2a85-m/OemCustomize.c
@@ -67,24 +67,24 @@
* 38 DP2_TX[P,N]6
*/
-static const PCIe_PORT_DESCRIPTOR PortList [] = {
+static const PCIe_PORT_DESCRIPTOR PortList[] = {
/* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23),
- PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
/* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
- PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
},
/* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */
{
DESCRIPTOR_TERMINATE_LIST,
- PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
- PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
+ PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
},
};
@@ -94,24 +94,24 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
* Tested and works: VGA/DVI
* Untested: HDMI
*/
-static const PCIe_DDI_DESCRIPTOR DdiList [] = {
+static const PCIe_DDI_DESCRIPTOR DdiList[] = {
// DP0 to HDMI0/DP
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
- PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1)
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1)
},
// DP1 to FCH
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
- PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
},
// DP2 to HDMI1/DP
{
0,
- PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35),
- PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3)
+ PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
+ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3)
},
};
@@ -211,22 +211,22 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
*/
static CONST PSO_ENTRY ROMDATA MemoryTable_M[] = {
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+ NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
+ NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
/*
TODO: is this OK for DDR3 socket FM2?
- MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
- CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
- ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
- CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
+ CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
+ ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
+ CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
*/
PSO_END
};
static CONST PSO_ENTRY ROMDATA MemoryTable_M_LE[] = {
- NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
- NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
+ NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1),
+ NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2),
PSO_END
};