summaryrefslogtreecommitdiff
path: root/src/mainboard/asus
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-04-27 00:14:05 +0200
committerFelix Held <felix-coreboot@felixheld.de>2020-05-02 18:56:00 +0000
commitfada3e56c4d896bcbf41280f0d20ed7c72000890 (patch)
treef2a62f182545bc4547203523161772cd9c71261e /src/mainboard/asus
parent76cedd2c292352d7dbd45fab70ec272e476d0910 (diff)
downloadcoreboot-fada3e56c4d896bcbf41280f0d20ed7c72000890.tar.xz
mb/asus/p8h61-m_pro: Fix function of pin 70
The board uses the pin for Deep S5, but the code was setting 3VSBSW. Change-Id: I81c865358002e6af500658efea851ab8c8202950 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/asus')
-rw-r--r--src/mainboard/asus/p8h61-m_pro/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb
index 0ad35776a9..ce6acadb8e 100644
--- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb
+++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb
@@ -90,7 +90,7 @@ chip northbridge/intel/sandybridge
irq 0xe5 = 0x06
irq 0xe6 = 0x0c
irq 0xe7 = 0x11
- irq 0xf0 = 0x20
+ irq 0xf0 = 0x00
irq 0xf2 = 0x5d
end
device pnp 2e.b on # HWM, LED