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authorRoy Mingi Park <roy.mingi.park@intel.com>2019-06-03 16:11:25 -0700
committerDuncan Laurie <dlaurie@chromium.org>2019-06-04 16:49:46 +0000
commit06cfb21e243ec74660e4886cef2f2e9c6c755d9e (patch)
tree19ec89696683d0864e5df4952a57e22b9f705e4c /src/mainboard/asus
parent13539d2f9d671099764f12e45b8e6d4e41c8e4af (diff)
downloadcoreboot-06cfb21e243ec74660e4886cef2f2e9c6c755d9e.tar.xz
mb/google/sarien: Fix SSD's power off sequence before going to S5
BUG=b:133389422 TEST=check SSD's power off sequence to meet PCIE requirement. SSD's reset should be cleared before clearing SSD's power EN Pin. Change-Id: Ia106b805deafb8a442b56bcce91b51135cb32988 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33182 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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