amdfam10 boards: Simplify early resourcemap

Purpose of the table is to load initial address maps
on PCI function 0:18.1. Provide a macro of its own so
it is clear no other PCI devfn is accessed here.

Change-Id: Ic146207580a5625c4f6799693157b02422bef00a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

6 files changed, 352 insertions, 352 deletions

diff --git a/src/mainboard/asus/kcma-d8/resourcemap.c b/src/mainboard/asus/kcma-d8/resourcemap.c
index 0edc3d1364..0dd0a9f12e 100644
--- a/src/mainboard/asus/kcma-d8/resourcemap.c
+++ b/src/mainboard/asus/kcma-d8/resourcemap.c
@@ -51,14 +51,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40 bit  address
 		 *	   that define the end of the DRAM region.
 		 */
-		// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
+		// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000,
+		ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
+		ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
+		ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
+		ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
+		ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
+		ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
+		ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
 
 		/* DRAM Base i Registers
 		 * F1:0x40 i = 0
@@ -90,14 +90,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40-bit address
 		 *	   that define the start of the DRAM region.
 		 */
-		// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
+		// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
 
 		/* Memory-Mapped I/O Limit i Registers
 		 * F1:0x84 i = 0
@@ -131,14 +131,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xBC), 0x00000048, 0x00000000,
 
 		/* Memory-Mapped I/O Base i Registers
 		 * F1:0x80 i = 0
@@ -166,14 +166,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40bit address
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000,
 
 		/* PCI I/O Limit i Registers
 		 * F1:0xC4 i = 0
@@ -200,10 +200,10 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */
+		ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
 
 		/* PCI I/O Base i Registers
 		 * F1:0xC0 i = 0
@@ -230,10 +230,10 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
+//		ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013,
+		ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
+		ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
+		ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
 
 		/* Config Base and Limit i Registers
 		 * F1:0xE0 i = 0
@@ -271,10 +271,10 @@ void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */
+		ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
 
 	};
 
@@ -306,14 +306,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40 bit  address
 		 *	   that define the end of the DRAM region.
 		 */
-		// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
+		// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000,
+		ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
+		ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
+		ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
+		ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
+		ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
+		ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
+		ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
 
 		/* DRAM Base i Registers
 		 * F1:0x40 i = 0
@@ -345,14 +345,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40-bit address
 		 *	   that define the start of the DRAM region.
 		 */
-		// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
+		// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
 
 		/* Memory-Mapped I/O Limit i Registers
 		 * F1:0x84 i = 0
@@ -386,14 +386,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xBC), 0x00000048, 0x00000000,
 
 		/* Memory-Mapped I/O Base i Registers
 		 * F1:0x80 i = 0
@@ -421,14 +421,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40bit address
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000,
 
 		/* PCI I/O Limit i Registers
 		 * F1:0xC4 i = 0
@@ -455,10 +455,10 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of CPU 0 --> AMD SR5690 */
+		ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
 
 		/* PCI I/O Base i Registers
 		 * F1:0xC0 i = 0
@@ -485,10 +485,10 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
+//		ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013,
+		ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
+		ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
+		ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
 
 		/* Config Base and Limit i Registers
 		 * F1:0xE0 i = 0
@@ -526,10 +526,10 @@ void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000203, /* link 2 of CPU 0 --> AMD SR5690 */
+		ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
 
 	};
 
diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c
index 3591488199..9efc60cb56 100644
--- a/src/mainboard/asus/kfsn4-dre/resourcemap.c
+++ b/src/mainboard/asus/kfsn4-dre/resourcemap.c
@@ -51,14 +51,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40 bit  address
 		 *	   that define the end of the DRAM region.
 		 */
-		// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
+		// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000,
+		ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
+		ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
+		ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
+		ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
+		ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
+		ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
+		ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
 
 		/* DRAM Base i Registers
 		 * F1:0x40 i = 0
@@ -90,14 +90,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40-bit address
 		 *	   that define the start of the DRAM region.
 		 */
-		// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
+		// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
 
 		/* Memory-Mapped I/O Limit i Registers
 		 * F1:0x84 i = 0
@@ -131,14 +131,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xBC), 0x00000048, 0x00000000,
 
 		/* Memory-Mapped I/O Base i Registers
 		 * F1:0x80 i = 0
@@ -166,14 +166,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40bit address
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000,
 
 		/* PCI I/O Limit i Registers
 		 * F1:0xC4 i = 0
@@ -200,10 +200,10 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> Nvidia CK 804 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> Nvidia CK 804 */
+		ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
 
 		/* PCI I/O Base i Registers
 		 * F1:0xC0 i = 0
@@ -230,10 +230,10 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
+//		ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013,
+		ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
+		ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
+		ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
 
 		/* Config Base and Limit i Registers
 		 * F1:0xE0 i = 0
@@ -271,10 +271,10 @@ void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> Nvidia CK 804 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> Nvidia CK 804 */
+		ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
 
 	};
 
diff --git a/src/mainboard/asus/kgpe-d16/resourcemap.c b/src/mainboard/asus/kgpe-d16/resourcemap.c
index b3c4465f87..cc3a23a4fd 100644
--- a/src/mainboard/asus/kgpe-d16/resourcemap.c
+++ b/src/mainboard/asus/kgpe-d16/resourcemap.c
@@ -51,14 +51,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40 bit  address
 		 *	   that define the end of the DRAM region.
 		 */
-		// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
+		// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000,
+		ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
+		ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
+		ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
+		ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
+		ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
+		ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
+		ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
 
 		/* DRAM Base i Registers
 		 * F1:0x40 i = 0
@@ -90,14 +90,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40-bit address
 		 *	   that define the start of the DRAM region.
 		 */
-		// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
+		// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
 
 		/* Memory-Mapped I/O Limit i Registers
 		 * F1:0x84 i = 0
@@ -131,14 +131,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xBC), 0x00000048, 0x00000000,
 
 		/* Memory-Mapped I/O Base i Registers
 		 * F1:0x80 i = 0
@@ -166,14 +166,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40bit address
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000,
 
 		/* PCI I/O Limit i Registers
 		 * F1:0xC4 i = 0
@@ -200,10 +200,10 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> AMD SR5690 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of CPU 0 --> AMD SR5690 */
+		ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
 
 		/* PCI I/O Base i Registers
 		 * F1:0xC0 i = 0
@@ -230,10 +230,10 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
+//		ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013,
+		ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
+		ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
+		ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
 
 		/* Config Base and Limit i Registers
 		 * F1:0xE0 i = 0
@@ -271,10 +271,10 @@ void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> AMD SR5690 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000103, /* link 1 of CPU 0 --> AMD SR5690 */
+		ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
 
 	};
 
@@ -306,14 +306,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40 bit  address
 		 *	   that define the end of the DRAM region.
 		 */
-		// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
+		// ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000,
+		ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
+		ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
+		ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
+		ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
+		ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
+		ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
+		ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
 
 		/* DRAM Base i Registers
 		 * F1:0x40 i = 0
@@ -345,14 +345,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40-bit address
 		 *	   that define the start of the DRAM region.
 		 */
-		// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
+		// ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
 
 		/* Memory-Mapped I/O Limit i Registers
 		 * F1:0x84 i = 0
@@ -386,14 +386,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xBC), 0x00000048, 0x00000000,
 
 		/* Memory-Mapped I/O Base i Registers
 		 * F1:0x80 i = 0
@@ -421,14 +421,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40bit address
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xB8), 0x000000f0, 0x00000000,
 
 		/* PCI I/O Limit i Registers
 		 * F1:0xC4 i = 0
@@ -455,10 +455,10 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of CPU 0 --> AMD SR5690 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of CPU 0 --> AMD SR5690 */
+		ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
 
 		/* PCI I/O Base i Registers
 		 * F1:0xC0 i = 0
@@ -485,10 +485,10 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
+//		ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00001013,
+		ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
+		ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
+		ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
 
 		/* Config Base and Limit i Registers
 		 * F1:0xE0 i = 0
@@ -526,10 +526,10 @@ void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000303, /* link 3 of CPU 0 --> AMD SR5690 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xE0), 0x0000FC88, 0x05000303, /* link 3 of CPU 0 --> AMD SR5690 */
+		ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
 
 	};
 
diff --git a/src/mainboard/asus/m4a78-em/resourcemap.c b/src/mainboard/asus/m4a78-em/resourcemap.c
index a4a1d9251a..e7a8cbf53f 100644
--- a/src/mainboard/asus/m4a78-em/resourcemap.c
+++ b/src/mainboard/asus/m4a78-em/resourcemap.c
@@ -49,14 +49,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40 bit  address
 		 *	   that define the end of the DRAM region.
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
+//		ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+		ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
+		ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
+		ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
+		ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
+		ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
+		ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
+		ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
 		/* DRAM Base i Registers
 		 * F1:0x40 i = 0
 		 * F1:0x48 i = 1
@@ -87,14 +87,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40-bit address
 		 *	   that define the start of the DRAM region.
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
+//		ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+		ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
 
 		/* Memory-Mapped I/O Limit i Registers
 		 * F1:0x84 i = 0
@@ -128,14 +128,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+		ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
+//		ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
 
 		/* Memory-Mapped I/O Base i Registers
 		 * F1:0x80 i = 0
@@ -163,14 +163,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40bit address
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
+		ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
+//		ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
 
 		/* PCI I/O Limit i Registers
 		 * F1:0xC4 i = 0
@@ -197,10 +197,10 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+//		ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000,
+		ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
 
 		/* PCI I/O Base i Registers
 		 * F1:0xC0 i = 0
@@ -227,10 +227,10 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
+//		ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003,
+		ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
+		ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
+		ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
 
 		/* Config Base and Limit i Registers
 		 * F1:0xE0 i = 0
@@ -268,10 +268,10 @@ void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration regin i
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+//		ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+		ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
 	};
 
 	int max;
diff --git a/src/mainboard/asus/m4a785-m/resourcemap.c b/src/mainboard/asus/m4a785-m/resourcemap.c
index a4a1d9251a..e7a8cbf53f 100644
--- a/src/mainboard/asus/m4a785-m/resourcemap.c
+++ b/src/mainboard/asus/m4a785-m/resourcemap.c
@@ -49,14 +49,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40 bit  address
 		 *	   that define the end of the DRAM region.
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
+//		ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+		ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
+		ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
+		ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
+		ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
+		ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
+		ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
+		ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
 		/* DRAM Base i Registers
 		 * F1:0x40 i = 0
 		 * F1:0x48 i = 1
@@ -87,14 +87,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40-bit address
 		 *	   that define the start of the DRAM region.
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
+//		ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+		ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
 
 		/* Memory-Mapped I/O Limit i Registers
 		 * F1:0x84 i = 0
@@ -128,14 +128,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+		ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
+//		ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
 
 		/* Memory-Mapped I/O Base i Registers
 		 * F1:0x80 i = 0
@@ -163,14 +163,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40bit address
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
+		ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
+//		ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
 
 		/* PCI I/O Limit i Registers
 		 * F1:0xC4 i = 0
@@ -197,10 +197,10 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+//		ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000,
+		ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
 
 		/* PCI I/O Base i Registers
 		 * F1:0xC0 i = 0
@@ -227,10 +227,10 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
+//		ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003,
+		ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
+		ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
+		ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
 
 		/* Config Base and Limit i Registers
 		 * F1:0xE0 i = 0
@@ -268,10 +268,10 @@ void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration regin i
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+//		ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+		ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
 	};
 
 	int max;
diff --git a/src/mainboard/asus/m5a88-v/resourcemap.c b/src/mainboard/asus/m5a88-v/resourcemap.c
index 94ada1e867..85ba50b8aa 100644
--- a/src/mainboard/asus/m5a88-v/resourcemap.c
+++ b/src/mainboard/asus/m5a88-v/resourcemap.c
@@ -47,14 +47,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40 bit  address
 		 *	   that define the end of the DRAM region.
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007,
+//		ADDRMAP_REG(0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+		ADDRMAP_REG(0x4C), 0x0000f8f8, 0x00000001,
+		ADDRMAP_REG(0x54), 0x0000f8f8, 0x00000002,
+		ADDRMAP_REG(0x5C), 0x0000f8f8, 0x00000003,
+		ADDRMAP_REG(0x64), 0x0000f8f8, 0x00000004,
+		ADDRMAP_REG(0x6C), 0x0000f8f8, 0x00000005,
+		ADDRMAP_REG(0x74), 0x0000f8f8, 0x00000006,
+		ADDRMAP_REG(0x7C), 0x0000f8f8, 0x00000007,
 		/* DRAM Base i Registers
 		 * F1:0x40 i = 0
 		 * F1:0x48 i = 1
@@ -85,14 +85,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40-bit address
 		 *	   that define the start of the DRAM region.
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000,
+//		ADDRMAP_REG(0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+		ADDRMAP_REG(0x48), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x50), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x58), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x60), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x68), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x70), 0x0000f8fc, 0x00000000,
+		ADDRMAP_REG(0x78), 0x0000f8fc, 0x00000000,
 
 		/* Memory-Mapped I/O Limit i Registers
 		 * F1:0x84 i = 0
@@ -126,14 +126,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upp address bits of a 40-bit address that
 		 *	   defines the end of a memory-mapped I/O region n
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
+		ADDRMAP_REG(0x84), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x8C), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x94), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0x9C), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xA4), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xAC), 0x00000048, 0x00000000,
+		ADDRMAP_REG(0xB4), 0x00000048, 0x00000000,
+//		ADDRMAP_REG(0xBC), 0x00000048, 0x00ffff00,
 
 		/* Memory-Mapped I/O Base i Registers
 		 * F1:0x80 i = 0
@@ -161,14 +161,14 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40bit address
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
+		ADDRMAP_REG(0x80), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x88), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x90), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0x98), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xA0), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xA8), 0x000000f0, 0x00000000,
+		ADDRMAP_REG(0xB0), 0x000000f0, 0x00000000,
+//		ADDRMAP_REG(0xB8), 0x000000f0, 0x00fc0003,
 
 		/* PCI I/O Limit i Registers
 		 * F1:0xC4 i = 0
@@ -195,10 +195,10 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
+//		ADDRMAP_REG(0xC4), 0xFE000FC8, 0x01fff000,
+		ADDRMAP_REG(0xCC), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xD4), 0xFE000FC8, 0x00000000,
+		ADDRMAP_REG(0xDC), 0xFE000FC8, 0x00000000,
 
 		/* PCI I/O Base i Registers
 		 * F1:0xC0 i = 0
@@ -225,10 +225,10 @@ void setup_mb_resource_map(void)
 		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
+//		ADDRMAP_REG(0xC0), 0xFE000FCC, 0x00000003,
+		ADDRMAP_REG(0xC8), 0xFE000FCC, 0x00000000,
+		ADDRMAP_REG(0xD0), 0xFE000FCC, 0x00000000,
+		ADDRMAP_REG(0xD8), 0xFE000FCC, 0x00000000,
 
 		/* Config Base and Limit i Registers
 		 * F1:0xE0 i = 0
@@ -266,10 +266,10 @@ void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration regin i
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
-		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
+//		ADDRMAP_REG(0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+		ADDRMAP_REG(0xE4), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xE8), 0x0000FC88, 0x00000000,
+		ADDRMAP_REG(0xEC), 0x0000FC88, 0x00000000,
 	};
 
 	int max;