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authorPaul Menzel <pmenzel@molgen.mpg.de>2020-04-27 13:55:47 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-06-06 09:45:00 +0000
commit9f7f92c7eedcddfde5800223a23d076a5e148a0e (patch)
tree11ac50e2184d5d777489c09c53f8a7ee4397f14d /src/mainboard/asus
parent76d55e5f00a02b69d300ae2d8f8f1851e9ad325a (diff)
downloadcoreboot-9f7f92c7eedcddfde5800223a23d076a5e148a0e.tar.xz
amd/agesa/hudson boards: Get rid of power button device
Port commit d7b88dcb (mb/google/x86-boards: Get rid of power button device in coreboot) to AMD AGESA Hudson boards. No idea, if this is correct for the two laptops. The Lenovo G505s also incorrectly defines two power buttons. [ 0.911423] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1 [ 0.911434] ACPI: Power Button [PWRB] [ 0.911493] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2 [ 0.912326] ACPI: Power Button [PWRF] If the generic power button device is needed, the POWER_BUTTON flag should be set in FADT. The GPE ACPI code seems to originate from commit 806def8c (I missed the svn add on r3787. These are the additional files., Add AMD dbm690t ACPI support.), and was copied over. Change-Id: I88950e15faf1b90ca6e688864bac40bf9779c32e Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Diffstat (limited to 'src/mainboard/asus')
-rw-r--r--src/mainboard/asus/f2a85-m/acpi/gpe.asl4
-rw-r--r--src/mainboard/asus/f2a85-m/dsdt.asl7
2 files changed, 0 insertions, 11 deletions
diff --git a/src/mainboard/asus/f2a85-m/acpi/gpe.asl b/src/mainboard/asus/f2a85-m/acpi/gpe.asl
index 69a5ccf8a6..30d10ce741 100644
--- a/src/mainboard/asus/f2a85-m/acpi/gpe.asl
+++ b/src/mainboard/asus/f2a85-m/acpi/gpe.asl
@@ -5,7 +5,6 @@ Scope(\_GPE) { /* Start Scope GPE */
/* General event 3 */
Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* Legacy PM event */
@@ -29,7 +28,6 @@ Scope(\_GPE) { /* Start Scope GPE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* ExtEvent0 SCI event */
@@ -47,13 +45,11 @@ Scope(\_GPE) { /* Start Scope GPE */
Method(_L18) {
/* DBGO("\\_GPE\\_L18\n") */
Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
/* Azalia SCI event */
Method(_L1B) {
/* DBGO("\\_GPE\\_L1B\n") */
Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
- Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
}
} /* End Scope GPE */
diff --git a/src/mainboard/asus/f2a85-m/dsdt.asl b/src/mainboard/asus/f2a85-m/dsdt.asl
index 6eb1c4fb1c..6234a009d9 100644
--- a/src/mainboard/asus/f2a85-m/dsdt.asl
+++ b/src/mainboard/asus/f2a85-m/dsdt.asl
@@ -38,13 +38,6 @@ DefinitionBlock (
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
#include "acpi/routing.asl"
- Device(PWRB) {
- Name(_HID, EISAID("PNP0C0C"))
- Name(_UID, 0xAA)
- Name(_PRW, Package () {3, 0x04})
- Name(_STA, 0x0B)
- }
-
Device(PCI0) {
/* Describe the AMD Northbridge */
#include <northbridge/amd/agesa/family15tn/acpi/northbridge.asl>