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authorJonathan A. Kollasch <jakllsch@kollasch.net>2015-07-20 09:51:34 -0500
committerJonathan A. Kollasch <jakllsch@kollasch.net>2015-07-23 18:30:19 +0200
commitacba73aefcbd7dacb547b61570a1836b745be2e5 (patch)
tree098ebd932670930651541536405d1f9b4548161d /src/mainboard/asus
parentff40196c6c5a83b7cf2ceeb2dd027d4f2587b94a (diff)
downloadcoreboot-acba73aefcbd7dacb547b61570a1836b745be2e5.tar.xz
nvidia southbridges: don't touch 0x78 in LPC bridge with Fam10h
Based on the observations that AMD Fam10h with both Nvidia CK804 (Asus KFSN4-DRE) and MCP55 (Sun Ultra 40 M2) need to avoid adjusting the LPC bridge register 0x78 (particularly the 0x7b byte) to get to ramstage: Assume that there's something about this register that adjusting it the way we do for K8 is something that can/should be universally avoided on all Fam10h systems with these chipsets. Change-Id: I1eceeb20ecaefef4c61c11e19d1f5a59f91a0a2f Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-on: http://review.coreboot.org/10984 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Diffstat (limited to 'src/mainboard/asus')
-rw-r--r--src/mainboard/asus/kfsn4-dre/romstage.c9
1 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
index aa72021d8d..cf36a7265c 100644
--- a/src/mainboard/asus/kfsn4-dre/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre/romstage.c
@@ -67,15 +67,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
-/*
- * Avoid crash (complete with severe memory corruption!) during initial CAR boot
- * in ck804_early_setup_x().
- * Interestingly once the system is fully booted into Linux this can be set, but
- * not before! Apparently something isn't initialized but the amount of effort
- * required to fix this is non-negligible and of unknown real-world benefit
- */
-#define CK804_SKIP_PCI_REG_78_INIT 1
-
#define CK804_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+33, ~(0x0f),(0x04 | 0x01), /* -ENOINFO Proprietary BIOS sets this register; "When in Rome..."*/