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| author | Tobias Diedrich <ranma+coreboot@tdiedrich.de> | 2010-12-08 21:40:12 +0000 |
|---|---|---|
| committer | Tobias Diedrich <ranma@tdiedrich.de> | 2010-12-08 21:40:12 +0000 |
| commit | b672d94ce0199bc0bd882c61c7be9ac2c90eded5 (patch) | |
| tree | 541e9563af928e193330b9e2d8b5cdda890749ae /src/mainboard/asus | |
| parent | 89ec3760a9c2e5189681240aae866b20a9d6b592 (diff) | |
| download | coreboot-b672d94ce0199bc0bd882c61c7be9ac2c90eded5.tar.xz | |
Tobias Diedrich wrote:
> Definitively a iasl problem, it can't even disassemble it's own
> output back to something equivalent to the input file.
> It seems to be generating Bytecode for the Add where it shouldn't.
Here is a solution using the SSDT.
Unfortunately iasl does not resolve simple arithmetic at compile
time, so we can not use Add(DEFAULT_PMBASE, PCNTRL) in the
Processor statement.
This patch instead dynamically generates the processor statement.
I can't use the speedstep generate_cpu_entries() directly since the
cpu doesn't support speedstep.
For now the code is in the southbridge directory, but maybe it
should go into cpu/intel/ somewhere.
IIRC notebook cpus of the era can already have speedstep, so it
would probably be possible to pair the i82371eb with a
speedstep-capable cpu...
Also, I don't know if multiprocessor boards (abit bp6?) would need
to be handled differently.
Abuild-tested.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6153 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/asus')
| -rw-r--r-- | src/mainboard/asus/p2b/dsdt.asl | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 7160054bf1..5e6411ce1b 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -21,15 +21,6 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) { - /* Define the main processor.*/ - Scope (\_PR) - { - /* Looks like the P_CNT field can't be a name or method (except - * builtins like Add()) and has to be hardcoded or generated - * into SSDT */ - Processor (CPU0, 0x01, Add(DEFAULT_PMBASE, PCNTRL), 0x06) {} - } - /* For now only define 2 power states: * - S0 which is fully on * - S5 which is soft off |