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authorKeith Hui <buurin@gmail.com>2017-09-01 19:55:49 -0400
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-09-21 15:29:49 +0000
commitaaa16fede70aaac56d1c835e663f52c4735826d8 (patch)
tree35b72d736a61528999a2ccacb02480618acaa316 /src/mainboard/avalue
parent402276574b9812c0e2d527ed50a3392439a97919 (diff)
downloadcoreboot-aaa16fede70aaac56d1c835e663f52c4735826d8.tar.xz
superio/winbond/*: Unify w*_set_clksel_48()
This function is identical throughout all Winbond superios in the tree, so move it into superio/winbond/common/early_init.c, renamed from early_serial.c because it now does more than just early serial. Change all affected mainboards to use the unified function. Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/avalue')
-rw-r--r--src/mainboard/avalue/eax-785e/romstage.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index d32e7b253d..e574ecdcb0 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_rs780_dev8();
sb800_clk_output_48Mhz();
- w83627hf_set_clksel_48(CLK_DEV);
+ winbond_set_clksel_48(CLK_DEV);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();