diff options
| author | Fabian Kunkel <fabi@adv.bruhnspace.com> | 2015-05-25 17:08:17 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-06-17 12:01:04 +0200 |
| commit | 7558dbac3179d51c78c092c12fe23a8ff8549496 (patch) | |
| tree | e3ed4d069146ff2edd836840ec6c4ce10f298d8f /src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c | |
| parent | 2a38551bb72765d37946c6f89fd48c0e9eec4580 (diff) | |
| download | coreboot-7558dbac3179d51c78c092c12fe23a8ff8549496.tar.xz | |
mainboard/bap: Add support for BAP ODE E20XX
Adding new board based on AMD Kabini.
Most of the code is copied from gizmosphere/gizmo2
Board is developed by BAP - Bruhnspace Advanced Projects:
http://www.unibap.com/ (Site is under construction)
Special on this board is:
-Soldered down memory
-SuperIO Fintek F81866D
Known bugs:
-S3 doesnt work
-Serial ports only works for the first boot. Needs power cut.
Tested with:
-SeaBios as Payload
-Linux OS - Lubuntu 14.10 32/64Bit, Kernel 3.19 - 4.1
-Windows 8 64Bit
Change-Id: I7e2b306620dd152a9f01ab6ccf2a0a880a068adb
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: http://review.coreboot.org/10288
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c')
| -rw-r--r-- | src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c b/src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c index 66bebc2ce5..a2826990f1 100644 --- a/src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c +++ b/src/mainboard/bap/ode_e20XX/PlatformGnbPcie.c @@ -32,7 +32,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, - HotplugDisabled, + HotplugBasic, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0x01, 0) @@ -42,7 +42,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, - HotplugDisabled, + HotplugBasic, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0x02, 0) @@ -72,7 +72,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1, - HotplugDisabled, + HotplugBasic, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0x05, 0) @@ -80,17 +80,17 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }; static const PCIe_DDI_DESCRIPTOR DdiList [] = { - /* DP0 to HDMI0/DP */ + /* eDP0 to LVDS connector*/ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) }, - /* DP1 to high-speed edge connector */ + /* DP1 to HDMI */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) }, }; |