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| author | Fabian Kunkel <fabi@adv.bruhnspace.com> | 2016-07-27 17:42:39 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-30 06:51:13 +0200 |
| commit | cf05183d1f952a903057038aee3a71698ce564b0 (patch) | |
| tree | f7e46a4f70131066396b7c519ba661c4a51e43c1 /src/mainboard/bap/ode_e21XX/OemCustomize.c | |
| parent | 171e2c965aef8b47d39611280121fd2b66136df4 (diff) | |
| download | coreboot-cf05183d1f952a903057038aee3a71698ce564b0.tar.xz | |
mainboard/bap/ode_e21XX: Add board support
Add next generation of BAPs (https://www.unibap.com/) SOC module,
called ode_e21XX.
Hardware is similar to e20XX (AMD G-Series GX-411GA Kabini),
but it includes a new AMD G-Series GX-412HC (Steppe Eagle)
and an updated Microsemi FPGA.
Changes to Olivehillplus:
- Add SuperIO Fintek F81866D
- Soldered down DDR3 with ECC
- User can choose between different DDR3 clk settings
(lowest setting can save up to 1.2W)
- Soldered down Microsemi M2S060 FPGA on PCIe lanes 2-3
Tested with:
- Payload SeaBIOS 1.9.1
- Lubuntu 16.04, Kernel 4.4.0
- Windows 10 (UART functionality)
Known problems:
- S3 not working
- IOMMU not working
Change-Id: I41f6a3334ad2128695a3f7c0a6444f1678d2626e
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15918
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/bap/ode_e21XX/OemCustomize.c')
| -rw-r--r-- | src/mainboard/bap/ode_e21XX/OemCustomize.c | 28 |
1 files changed, 6 insertions, 22 deletions
diff --git a/src/mainboard/bap/ode_e21XX/OemCustomize.c b/src/mainboard/bap/ode_e21XX/OemCustomize.c index ac60c42082..3750ba4305 100644 --- a/src/mainboard/bap/ode_e21XX/OemCustomize.c +++ b/src/mainboard/bap/ode_e21XX/OemCustomize.c @@ -18,20 +18,10 @@ #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { - /* Initialize Port descriptor (PCIe port, Lane 3, PCI Device 2, Function 5) */ + /* Initialize Port descriptor (PCIe port, Lanes 2-3, PCI Device 2, Function 4) */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, - HotplugDisabled, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x01, 0) - }, - /* Initialize Port descriptor (PCIe port, Lane 2, PCI Device 2, Function 4) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 3), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, HotplugDisabled, PcieGenMaxSupported, @@ -71,23 +61,17 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { }; static const PCIe_DDI_DESCRIPTOR DdiList [] = { - /* DP0 to HDMI0/DP */ + /* eDP0 to LVDS connector */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) }, - /* DP1 to FCH */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) - }, - /* DP2 to HDMI1/DP */ + /* DP1 to HDMI */ { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3) + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) }, }; |