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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2020-03-20 13:56:46 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-25 10:43:37 +0000 |
| commit | 9550e97304ecc1c1b6271d50ea089c82b9a82946 (patch) | |
| tree | 47d39123eae170fe1a014b8bdde8d96a17f7943c /src/mainboard/bap | |
| parent | a956063e5f9c19179e4bacd145e26e159f1982b2 (diff) | |
| download | coreboot-9550e97304ecc1c1b6271d50ea089c82b9a82946.tar.xz | |
acpi: correct the processor devices scope
The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here.
Additionally add processor scope patching for P-State SSDT created by
AGESA, becasue AGESA creates the tables with processors in \_PR scope.
TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are
no errors, decompile ACPI tables with acpica to check whether the
processor scope is correct and if IASL does not complain on wrong
checksum, run FWTS
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/bap')
| -rw-r--r-- | src/mainboard/bap/ode_e20XX/dsdt.asl | 2 | ||||
| -rw-r--r-- | src/mainboard/bap/ode_e21XX/dsdt.asl | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/bap/ode_e20XX/dsdt.asl b/src/mainboard/bap/ode_e20XX/dsdt.asl index a7914191d0..15b241f897 100644 --- a/src/mainboard/bap/ode_e20XX/dsdt.asl +++ b/src/mainboard/bap/ode_e20XX/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include <cpu/amd/agesa/family16kb/acpi/cpu.asl> /* Contains the supported sleep states for this chipset */ diff --git a/src/mainboard/bap/ode_e21XX/dsdt.asl b/src/mainboard/bap/ode_e21XX/dsdt.asl index 4bf4dc8276..8440ecaa0f 100644 --- a/src/mainboard/bap/ode_e21XX/dsdt.asl +++ b/src/mainboard/bap/ode_e21XX/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock ( /* PCI IRQ mapping for the Southbridge */ #include <southbridge/amd/pi/hudson/acpi/pcie.asl> - /* Describe the processor tree (\_PR) */ + /* Describe the processor tree (\_SB) */ #include <cpu/amd/pi/00730F01/acpi/cpu.asl> /* Contains the supported sleep states for this chipset */ |