diff options
| author | Fabian Kunkel <fabi@adv.bruhnspace.com> | 2016-07-26 22:11:07 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-31 19:58:12 +0200 |
| commit | 1f9c07fcd735e2e55104d1b3a2672298a460d5fb (patch) | |
| tree | cc6a9749cf7fc1e3765191439f15506fb874ab5c /src/mainboard/bap | |
| parent | 449fb9b6eb886a6bd364f9f5c5617e30152c013d (diff) | |
| download | coreboot-1f9c07fcd735e2e55104d1b3a2672298a460d5fb.tar.xz | |
mainboard/bap/ode_e20XX: Change PCIe lines
This patch binds PCIe lanes 2 and 3 to one PCIe device.
PCIe device 2.4 becomes x2.
Tested with the connected FPGA on PCIe 2.4.
FPGA doubles transfer rate from/to the AMD.
Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0
Change-Id: Icee567272312a7df4c3b5a6db5b420a054ec3230
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15905
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/bap')
| -rw-r--r-- | src/mainboard/bap/ode_e20XX/OemCustomize.c | 19 | ||||
| -rw-r--r-- | src/mainboard/bap/ode_e20XX/devicetree.cb | 3 |
2 files changed, 6 insertions, 16 deletions
diff --git a/src/mainboard/bap/ode_e20XX/OemCustomize.c b/src/mainboard/bap/ode_e20XX/OemCustomize.c index 7feab3a4cb..752293a031 100644 --- a/src/mainboard/bap/ode_e20XX/OemCustomize.c +++ b/src/mainboard/bap/ode_e20XX/OemCustomize.c @@ -25,26 +25,17 @@ #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { + /* Initialize Port descriptor (PCIe port, Lanes 2-3, PCI Device Number 2, Function 4) */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3), - PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5, - HotplugBasic, - PcieGenMaxSupported, - PcieGenMaxSupported, - AspmDisabled, 0x01, 0) - }, - /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2), + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 3), PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4, HotplugBasic, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0x02, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ + /* Initialize Port descriptor (PCIe port, Lane 1, PCI Device Number 2, Function 3) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1), @@ -54,7 +45,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { PcieGenMaxSupported, AspmDisabled, 0x03, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ + /* Initialize Port descriptor (PCIe port, Lane 0, PCI Device Number 2, Function 2) */ { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0), @@ -64,7 +55,7 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { PcieGenMaxSupported, AspmDisabled, 0x04, 0) }, - /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ + /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2, Function 1) */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), diff --git a/src/mainboard/bap/ode_e20XX/devicetree.cb b/src/mainboard/bap/ode_e20XX/devicetree.cb index a598a995ed..3e0272c0e4 100644 --- a/src/mainboard/bap/ode_e20XX/devicetree.cb +++ b/src/mainboard/bap/ode_e20XX/devicetree.cb @@ -31,8 +31,7 @@ chip northbridge/amd/agesa/family16kb/root_complex device pci 2.1 on end # x4 PCIe Slot device pci 2.2 on end # PCIe Q7 Realtek GBit LAN device pci 2.3 on end # PCIe CB Realtek GBit LAN - device pci 2.4 on end # PCIe BAP FPGA - device pci 2.5 on end # PCIe BAP FPGA (unused, for 050T) + device pci 2.4 on end # x2 PCIe Microsemi FPGA end #chip northbridge/amd/agesa/family16kb chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus |