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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-03 12:36:09 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-09 05:23:55 +0000 |
| commit | 657d68bddc030e38bc19eb4eef07f59b5e5258e4 (patch) | |
| tree | 90d064a1e09721ae2e9279117ecb71f8ede854eb /src/mainboard/bap | |
| parent | dafc78bb8d6bda8bddb029168491365b333ce529 (diff) | |
| download | coreboot-657d68bddc030e38bc19eb4eef07f59b5e5258e4.tar.xz | |
AGESA,binaryPI: Move PORT80 selection to C bootblock
Because the function is implemented in C, post_code() calls
from cache_as_ram.S and other early assembly entry files may
not currently work for cold boots. Assembly implementation
needs to follow one day.
This effectively removes PORT80 routing from boards with
ROMCC_BOOTBLOCK.
Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src/mainboard/bap')
| -rw-r--r-- | src/mainboard/bap/ode_e20XX/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/bap/ode_e20XX/romstage.c | 2 | ||||
| -rw-r--r-- | src/mainboard/bap/ode_e21XX/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/bap/ode_e21XX/romstage.c | 2 |
4 files changed, 2 insertions, 4 deletions
diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index a62fba82da..97593d5d78 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c index ef7a7fb65b..505de38d9e 100644 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ b/src/mainboard/bap/ode_e20XX/romstage.c @@ -36,7 +36,5 @@ void board_BeforeAgesa(struct sysinfo *cb) pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); - fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index 3705fb9615..bc5c131f79 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -25,6 +25,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index e58f875f2f..de39f18a75 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -41,8 +41,6 @@ static void romstage_main_template(void) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); |