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authorStefan Reinauer <stefan.reinauer@coreboot.org>2016-05-04 13:24:47 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2016-05-05 20:08:58 +0200
commit3b0f20ba70e7c42e233c1db0bdafed4da7b2483d (patch)
tree5c43e4fb25b05c788ca40c7c3e60c0c96c8bc5a7 /src/mainboard/bifferos
parent5caf89b9f848bbab199e7e6bd37897f6464e4d23 (diff)
downloadcoreboot-3b0f20ba70e7c42e233c1db0bdafed4da7b2483d.tar.xz
rdc/r8610: Move to src/soc
Change-Id: I99e5d7f3b46c90ca863ddf6c186b5447d0c8e6f2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/14607 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/bifferos')
-rw-r--r--src/mainboard/bifferos/bifferboard/Kconfig8
-rw-r--r--src/mainboard/bifferos/bifferboard/devicetree.cb6
2 files changed, 3 insertions, 11 deletions
diff --git a/src/mainboard/bifferos/bifferboard/Kconfig b/src/mainboard/bifferos/bifferboard/Kconfig
index cf08ac8b9a..c65b02ffa2 100644
--- a/src/mainboard/bifferos/bifferboard/Kconfig
+++ b/src/mainboard/bifferos/bifferboard/Kconfig
@@ -2,14 +2,8 @@ if BOARD_BIFFEROS_BIFFERBOARD
config BOARD_SPECIFIC_OPTIONS
def_bool y
- select ARCH_BOOTBLOCK_X86_32
- select ARCH_VERSTAGE_X86_32
- select ARCH_ROMSTAGE_X86_32
- select ARCH_RAMSTAGE_X86_32
- select ROMCC
select BOARD_ROMSIZE_KB_128
- select NORTHBRIDGE_RDC_R8610
- select SOUTHBRIDGE_RDC_R8610
+ select SOC_RDC_R8610
config MAINBOARD_DIR
string
diff --git a/src/mainboard/bifferos/bifferboard/devicetree.cb b/src/mainboard/bifferos/bifferboard/devicetree.cb
index 09dde33517..a64b138cb0 100644
--- a/src/mainboard/bifferos/bifferboard/devicetree.cb
+++ b/src/mainboard/bifferos/bifferboard/devicetree.cb
@@ -1,8 +1,6 @@
-chip northbridge/rdc/r8610
+chip soc/rdc/r8610
device domain 0 on
device pci 0.0 on end
- chip southbridge/rdc/r8610 # Southbridge
- device pci 7.0 on end # SB
- end
+ device pci 7.0 on end # SB
end
end