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author | Damien Zammit <damien@zamaudio.com> | 2017-10-04 20:07:47 +1100 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-10-14 08:00:34 +0000 |
commit | d2b5b734e8d303f35f99523809e3b1044fe5f203 (patch) | |
tree | db3ce4c04fd60a9c0ff00496b7f28239cf2da147 /src/mainboard/biostar/a68n_5200/romstage.c | |
parent | 66030fa5ab35ac54b2569532a36c6baacc0bde40 (diff) | |
download | coreboot-d2b5b734e8d303f35f99523809e3b1044fe5f203.tar.xz |
biostar/a68n_5200: Clone amd/olivehill
Altered Kconfig board names to make it pass lint
Change-Id: I9ccfe014a0e3a70148463fc9f8de02b500fac69e
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/biostar/a68n_5200/romstage.c')
-rw-r--r-- | src/mainboard/biostar/a68n_5200/romstage.c | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c new file mode 100644 index 0000000000..8190cb7711 --- /dev/null +++ b/src/mainboard/biostar/a68n_5200/romstage.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <commonlib/loglevel.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <southbridge/amd/agesa/hudson/hudson.h> + +void board_BeforeAgesa(struct sysinfo *cb) +{ + int i; + u32 val; + + /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA + * even though the register is not documented in the Kabini BKDG. + * Otherwise the serial output is bad code. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + outb(0xea, 0xcd6); + outb(0x1, 0xcd7); + + /* Set LPC decode enables. */ + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); + + hudson_lpc_port80(); + + /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ + for (i = 0; i < 200000; i++) + val = inb(0xcd6); +} |