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| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2016-09-27 11:55:24 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-01 17:38:16 +0200 |
| commit | 62a193899c84aa46a7c06292fac55e4c6531f1a4 (patch) | |
| tree | 88edc180b55cdea9f0dfe4d6bd340a9bdfca8f6d /src/mainboard/biostar/am1ml/romstage.c | |
| parent | c6452bb8c539e4108191f35830a366f82163c877 (diff) | |
| download | coreboot-62a193899c84aa46a7c06292fac55e4c6531f1a4.tar.xz | |
mainboard/google/reef: Update DPTF policy temp. values for CPU
This patch increases the CPU specific passive temp. trip point
and critical temp. trip point value for DPTF policy.
BUG=chrome-os-partner:57903
TEST=Built, booted on reef and verified this passive and
critical temp. trip points with heavy workload.
Change-Id: I2a38d01a6539c1bd478f8716c4b543ebcd1f2080
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/16766
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Diffstat (limited to 'src/mainboard/biostar/am1ml/romstage.c')
0 files changed, 0 insertions, 0 deletions