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authorElyes HAOUAS <ehaouas@noos.fr>2016-09-26 21:11:58 +0200
committerMartin Roth <martinroth@google.com>2016-09-28 22:07:19 +0200
commitd9ceae5f205574020a280edd6917f5689f94423d (patch)
treeb090970d9aad470be3eea5030a97cf606e1784e4 /src/mainboard/broadcom/blast
parent28821dbb2261267462a7e9b0cc1c23b51af2d3ee (diff)
downloadcoreboot-d9ceae5f205574020a280edd6917f5689f94423d.tar.xz
mainboard/broadcom/blast: Use tabs for indents
Change-Id: I61bef70ec572c12518cd3763a6a860e56bfdb716 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16745 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/broadcom/blast')
-rw-r--r--src/mainboard/broadcom/blast/romstage.c48
1 files changed, 24 insertions, 24 deletions
diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c
index e687c2e054..33d939a71a 100644
--- a/src/mainboard/broadcom/blast/romstage.c
+++ b/src/mainboard/broadcom/blast/romstage.c
@@ -28,13 +28,13 @@ static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x71
- unsigned device=(ctrl->channel0[0])>>8;
- smbus_send_byte(SMBUS_HUB, device);
+ unsigned device=(ctrl->channel0[0])>>8;
+ smbus_send_byte(SMBUS_HUB, device);
}
static inline int spd_read_byte(unsigned device, unsigned address)
{
- return smbus_read_byte(device, address);
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdk8/raminit.c"
@@ -52,52 +52,52 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
- RC0|DIMM0, RC0|DIMM2, 0, 0,
- RC0|DIMM1, RC0|DIMM3, 0, 0,
- RC1|DIMM0, RC1|DIMM2, 0, 0,
- RC1|DIMM1, RC1|DIMM3, 0, 0,
+ RC0|DIMM0, RC0|DIMM2, 0, 0,
+ RC0|DIMM1, RC0|DIMM3, 0, 0,
+ RC1|DIMM0, RC1|DIMM2, 0, 0,
+ RC1|DIMM1, RC1|DIMM3, 0, 0,
};
- int needs_reset;
+ int needs_reset;
unsigned bsp_apicid = 0, nodes;
- struct mem_controller ctrl[8];
+ struct mem_controller ctrl[8];
- if (!cpu_init_detectedx && boot_cpu()) {
+ if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
bcm5785_enable_lpc();
pc87417_enable_dev(RTC_DEV); /* Enable RTC */
- }
+ }
- if (bist == 0)
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
+ console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
- setup_blast_resource_map();
+ setup_blast_resource_map();
#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 0));
+ dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
needs_reset = setup_coherent_ht_domain();
#if CONFIG_LOGICAL_CPUS
- // It is said that we should start core1 after all core0 launched
- wait_all_core0_started();
- start_other_cores();
+ // It is said that we should start core1 after all core0 launched
+ wait_all_core0_started();
+ start_other_cores();
#endif
- wait_all_aps_started(bsp_apicid);
+ wait_all_aps_started(bsp_apicid);
- needs_reset |= ht_setup_chains_x();
+ needs_reset |= ht_setup_chains_x();
bcm5785_early_setup();
@@ -108,9 +108,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
allow_all_aps_stop(bsp_apicid);
- nodes = get_nodes();
- //It's the time to set ctrl now;
- fill_mem_ctrl(nodes, ctrl, spd_addr);
+ nodes = get_nodes();
+ //It's the time to set ctrl now;
+ fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus();
@@ -121,7 +121,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(nodes, ctrl);
#if 0
- print_pci_devices();
+ print_pci_devices();
dump_pci_devices();
#endif