cavium: Add CN81xx SoC and eval board support

This adds Cavium CN81xx SoC and SFF EVB files.

Code is based off of Cavium's Octeon-TX SDK:
https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK

BDK coreboot differences:
bootblock:
- Get rid of BDK header
- Add Kconfig for link address
- Move CAR setup code into assembly
- Move unaligned memory access enable into assembly
- Implement custom bootblock entry function
- Add CLIB and CSIB blobs

romstage:
- Use minimal DRAM init only

devicetree:
- Convert FTD to static C file containing key value pairs

Tested on CN81xx:
- Boots to payload
- Tested with GNU/Linux 4.16.3
- All hardware is usable (after applying additional commits)

Implemented in future commits:
- Vboot integration
- MMU suuport
- L2 Cache handling
- ATF from external repo
- Devicetree patching
- Extended DRAM testing
- UART init

Not working:
- Booting a payload
- Booting upstream ATF

TODO:
- Configuration straps

Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688
Signed-off-by: David Hendricks <dhendricks@fb.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/23037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

1 files changed, 46 insertions, 0 deletions

diff --git a/src/mainboard/cavium/cn8100_sff_evb/bootblock.c b/src/mainboard/cavium/cn8100_sff_evb/bootblock.c
new file mode 100644
index 0000000000..36332cc6e3
--- /dev/null
+++ b/src/mainboard/cavium/cn8100_sff_evb/bootblock.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <soc/soc.h>
+#include <soc/spi.h>
+#include <soc/uart.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
+		if (!uart_is_enabled(0))
+			uart_setup(0, CONFIG_TTYS0_BAUD);
+		if (!uart_is_enabled(1))
+			uart_setup(0, CONFIG_TTYS0_BAUD);
+	}
+}
+
+static void configure_spi_flash(void)
+{
+	/* FIXME: Only tested on EM100 Pro */
+	spi_init_custom(0, // bus
+			25000000, // speed Hz
+			0, // idle low disabled
+			0, // zero idle cycles between transfers
+			0, // MSB first
+			0, // Chip select 0
+			1); // assert is high
+}
+
+void bootblock_mainboard_init(void)
+{
+	configure_spi_flash();
+}