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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-02-14 15:18:14 -0800 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-02-17 18:45:28 +0100 |
| commit | 7fcaf77c2ddb622a1a15c6d49d2f7a550ae6bd6e (patch) | |
| tree | 7d37336d6805ce8c3db3621875961c4a2ce6fc78 /src/mainboard/compaq | |
| parent | 2e8117143a695b5331f9c79eeb77bb870db407b3 (diff) | |
| download | coreboot-7fcaf77c2ddb622a1a15c6d49d2f7a550ae6bd6e.tar.xz | |
mainboard/intel/galileo: Disable the remaining PCI devices
Add additional lines to the devicetree.cb file to disable the PCI
devices in the Quark SoC.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* Devices show up as disabled in BS_DEV_ENUMERATE state or ramstage
Change-Id: I1edbbcb88cef29ce972ef054c82e37bf07c3761d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13720
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/compaq')
0 files changed, 0 insertions, 0 deletions