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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-06-16 23:29:23 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 09:00:57 +0000 |
| commit | 6beaef983aee5d886f6f8571855a92d608d98a17 (patch) | |
| tree | 9c7f858bc7baa36d9e18ed84ea61d742559922c2 /src/mainboard/compulab/intense_pc | |
| parent | 4821a0e135ff2d60f552203d2724ae2d44850623 (diff) | |
| download | coreboot-6beaef983aee5d886f6f8571855a92d608d98a17.tar.xz | |
sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetree
Set up generic decode ranges based on the devicetree settings.
Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/compulab/intense_pc')
| -rw-r--r-- | src/mainboard/compulab/intense_pc/romstage.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/compulab/intense_pc/romstage.c b/src/mainboard/compulab/intense_pc/romstage.c index 6d0b3af8c0..6c3d980b65 100644 --- a/src/mainboard/compulab/intense_pc/romstage.c +++ b/src/mainboard/compulab/intense_pc/romstage.c @@ -33,12 +33,6 @@ void pch_enable_lpc(void) u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN; pci_write_config16(dev, LPC_EN, lpc_config); - /* Map 1 byte to the LPC bus. */ - pci_write_config32(dev, LPC_GEN1_DEC, 0x00164d); - - /* Map a range for the runtime_port registers to the LPC bus. */ - pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181); - #if CONFIG(DRIVERS_UART_8250IO) /* Enable COM1 */ if (sio1007_enable_uart_at(SIO_PORT)) { |